This Non-provisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2004-123450 filed in Japan on Apr. 19, 2004, the entire contents of which are hereby incorporated by reference.
The present invention relates to a method for characterizing the characteristics of cells subjected to a delay time calculation with consideration for a waveform distortion in a semiconductor integrated circuit, which is provided for the purpose of performing a circuit design with consideration for a waveform distortion. The present invention further relates to a delay time calculation method using the characterization method.
In a general cell characteristic characterization method used in the preparation of a library for gate-level delay time calculation, various values of the input transition value and drive load are assigned to a cell subjected to a characterization (characterization subject cell), and the output transition value which represents the slope of a waveform at an output terminal and the cell delay time are measured. The output transition value and the value of the cell delay time are formatted in a two-dimensional table of the input transition value and the drive load which are to be assigned to a cell, whereby the characteristics of the cell are characterized and converted to a library.
Referring to the two-dimensional table of the input transition value and drive load, which is shown in
IEICE Technical Report (Shingakugiho) VLD98-137 discloses an example of the delay time calculation method which uses the two-dimensional delay time table. According to this method, in the first place, the capacitance driven by a cell is obtained as an effective capacitance and, thereafter, a library generated by a two-dimensional delay time table of the input transition value and the drive load is referred to determine a delay time which corresponds to the input transition value assigned to the cell and the value of the previously-obtained effective capacitance (drive load), whereby the delay time of the cell is calculated.
Japanese Unexamined Patent Publication No. 2001-67387 proposes another delay time calculation method, which is used when a waveform input to a cell has a distortion. In this method, a nonlinear signal waveform input to the cell is subjected to a linear approximation as a group of linear signal waveforms, and a result of the linear approximation is used to perform a delay time calculation.
In a post-layout circuit modification which uses the above-described conventional delay time calculation method, setup verification and hold verification are performed based on a result of the delay time calculation. A path which can cause a malfunction due to an early arrival of a signal is subjected to a delay time adjustment process by means of buffer insertion, or the like. As for a path which can causes a malfunction due to a late arrival of a signal, the driving capacity of a cell in the path is increased, for example.
However, there is a possibility that distortion occurs in a signal waveform input to/output from each cell according to the relationship between the driving capacity of the cell and the drive capacitance. Nevertheless, the delay time calculation method described in IEICE Technical Report VLD98-137 fails to consider such a case and is based on the premise that no distortion occurs in the input waveform. Thus, the calculation result includes an error when waveform distortion occurs as described above.
Especially when waveform distortion occurs in the vicinity of the threshold of delay measurement due to the above-described reason, a cell characteristic extraction result greatly differs from an actual result, and accordingly, the accuracy of delay time calculation deteriorates.
In the delay time calculation method described in Japanese Unexamined Patent Publication No. 2001-67387, distortion in the waveform input to a cell is considered for improving the calculation accuracy, but the influence of distortion in the waveform which occurs depending on the size of the capacitance driven by the cell is not considered. Therefore, when distortion occurs due to such a reason, the calculation result includes an error.
Further, also when the above conventional delay time calculation methods are used in a post-layout circuit modification, distortion occurs in the waveform input to/output from a cell in actuality, and therefore, the actual delay time can be longer than calculated. In such a case, for example, an additional effort of modifying a circuit is required in a hold error correction process. Further, the above calculation error can result in missing an error in a setup error correction process.
An objective of the present invention is to realize an accurate delay time calculation with consideration for a cause of distortion which occurs in a waveform input to/output from a circuit that is subjected to delay time calculation due to the size of the drive load driven by a cell and the slope waveform input to the cell.
In order to achieve the above objective, according to the present invention, specific circuit conditions obtained when an input/output waveform includes distortion are extracted as parameters for a slope waveform input to a delay time calculation subject circuit and the drive load which is driven by the delay time calculation subject circuit. Further, the relationship of these parameters is converted to a library. The library is referred to in an actual delay time calculation, whereby a correct output waveform and a delay value are calculated from the input slope waveform and the drive load. The library is also referred to when a post-layout circuit modification is performed, whereby the influence of waveform distortion is considered.
One aspect of the present invention is directed to a cell characteristic characterization method for characterizing the characteristics of a cell to which a predetermined drive load is connected, where an input waveform to the cell has a distortion due to the Miller effect, the method comprising: an effective input terminal capacitance calculation step of calculating an effective input terminal capacitance of the cell which corresponds to a case where the input waveform input to the characterization subject cell to which the drive load is connected results in a distorted waveform which is delayed from the input waveform by a predetermined delay time due to the Miller effect; and a storage step of storing the effective input terminal capacitance calculated at the effective input terminal capacitance calculation step as a function of the input waveform and the value of the drive load.
Another aspect of the present invention is directed to a cell characteristic characterization method, comprising: an input slope waveform generation step of generating an input slope waveform; an input bump waveform generation step of generating an input bump waveform; a circuit simulation step of inputting an input waveform which includes the input slope waveform and the input bump waveform superimposed thereon to the characterization subject cell and measuring an output waveform of the characterization subject cell which corresponds to the input waveform input to the characterization subject cell; a slope waveform/bump waveform separation step of separating the measured output waveform of the characterization subject cell into an output slope waveform and an output bump waveform; and a storage step of storing the output slope waveform and the output bump waveform as a function of the input slope waveform and the input bump waveform.
In one embodiment of the present invention, each of the input bump waveform and the output bump waveform is defined by a waveform transition time of the slope waveform, a bump waveform height, a bump waveform width, a bump area, a time interval which elapses till the bump waveform reaches a peak, and a timing at which the bump waveform is superimposed on the slope waveform.
Still another aspect of the present invention is directed to a cell characteristic characterization method for characterizing a characterization subject cell to which a predetermined drive load is connected, a cell which has a small driving capacity being connected to an input side of the characterization subject cell, the method comprising: a waveform distortion detection step which includes inputting an input waveform to the small driving capacity cell, and detecting the presence/absence of a waveform distortion in an input waveform and an output waveform of the characterization subject cell as a result of the input waveform to the small driving capacity cell; and a storage step of storing the presence/absence of the waveform distortion in the input waveform and the output waveform of the characterization subject cell as a function or table of the input waveform of the characterization subject cell and the value of the drive load.
Still another aspect of the present invention is directed to a delay time calculation method for calculating a delay time of a semiconductor integrated circuit with consideration for a waveform distortion using the above-described cell characteristic characterization method, the semiconductor integrated circuit including a plurality of cells connected by a plurality of lines, the method comprising: a drive load/input waveform extraction step of extracting an input waveform and a value of a drive load as to a delay time calculation subject cell selected from the plurality of cells; a distortion-generating pattern determination step of referring to the function of the above-described cell characteristic characterization method to determine whether or not a pattern of the delay time calculation subject cell which corresponds to the extracted input waveform and the extracted value of the drive load generates a distortion in the input waveform or the output waveform; if the pattern is not determined to be a pattern which generates a distortion at the distortion-generating pattern determination step, a gate-level delay time calculation step of performing a gate-level delay time calculation process on the delay time calculation subject cell; and if the pattern is determined to be a pattern which generates a distortion at the distortion-generating pattern determination step, a transistor-level delay time calculation step of performing a transistor-level delay time calculation process on the delay time calculation subject cell.
In one embodiment of the present invention, the delay time calculation method further comprises a waveform distortion detection step, which includes detecting whether or not a waveform distortion occurs in an input waveform and an output waveform of the delay time calculation subject cell after the delay time calculation at the transistor-level delay time calculation step, and if a waveform distortion occurs, repeating a transistor-level delay time calculation at the transistor-level delay time calculation step till the occurrence of the waveform distortion is stopped.
Still another aspect of the present invention is directed to a delay time calculation method for calculating a delay time of a semiconductor integrated circuit with consideration for a waveform distortion, the semiconductor integrated circuit including a plurality of instances connected by a plurality of nets, the method comprising: a first delay time calculation step of calculating a delay time of all the instances and a line delay time of all the nets and signal waveforms at input and output terminals of all the instances; an instance input signal waveform calculation step of obtaining a distorted input signal waveform which is distorted due to the Miller effect of a delay time calculation subject instance selected from the plurality of instances, the instance input signal waveform calculation step including inputting a variable input terminal capacitance value of the delay time calculation subject instance which is determined according to the presence/absence of a distortion caused by the Miller effect in an input waveform, representing the variable input terminal capacitance value as a coupling capacitance between input and output terminals of the delay time calculation subject instance, and calculating crosstalk using a net connected to the output terminal of the delay time calculation subject instance as an aggressor and a net connected to the input terminal of the delay time calculation subject instance as a victim; an instance output signal waveform transfer step of obtaining a distorted output signal waveform of the delay time calculation subject instance, the instance output signal waveform transfer step including inputting the distorted input signal waveform calculated at the instance input signal waveform calculation step, and calculating a signal waveform transfer between the input and output terminals of the delay time calculation subject instance; and a second delay time calculation step which includes calculating a delay time of the delay time calculation subject instance based on the distorted input signal waveform and the distorted output signal waveform of the delay time calculation subject instance, and allowing transfer of the distorted output signal waveform to calculate a delay time of a subsequent instance and a line delay time of a subsequent net.
Still another aspect of the present invention is directed to a delay time calculation method for calculating a delay time of a semiconductor integrated circuit with consideration for a waveform distortion, the semiconductor integrated circuit including a plurality of instances connected by a plurality of nets, the method comprising: a first delay time calculation step of calculating a delay time of all the instances and a line delay time of all the nets and signal waveforms at input and output terminals of all the instances; an instance input signal waveform calculation step of obtaining a distorted input signal waveform which is distorted due to the Miller effect of a delay time calculation subject instance selected from the plurality of instances, the instance input signal waveform calculation step including inputting a variable input terminal capacitance value of the delay time calculation subject instance which is determined according to the presence/absence of a distortion caused by the Miller effect in an input waveform, representing the variable input terminal capacitance value as a coupling capacitance between input and output terminals of the delay time calculation subject instance, and calculating crosstalk using a net connected to the output terminal of the delay time calculation subject instance as an aggressor and a net connected to the input terminal of the delay time calculation subject instance as a victim; an instance output signal waveform calculation step of obtaining a distorted output signal waveform which is distorted due to the Miller effect of the delay time calculation subject instance, the instance output signal waveform calculation step including inputting the variable input terminal capacitance value, representing the variable input terminal capacitance value as a coupling capacitance between the input and output terminals of the delay time calculation subject instance, and calculating crosstalk using a net connected to the input terminal of the delay time calculation subject instance as an aggressor and a net connected to the output terminal of the delay time calculation subject instance as a victim; a second delay time calculation step which includes calculating a delay time of the delay time calculation subject instance based on the distorted input signal waveform and the distorted output signal waveform of the delay time calculation subject instance, and allowing transfer of the distorted output signal waveform to calculate a delay time of a subsequent instance and a line delay time of a subsequent net.
Still another aspect of the present invention is directed to a delay time calculation method for calculating a delay time of a semiconductor integrated circuit with consideration for a waveform distortion using the above-described cell characteristic characterization method, the semiconductor integrated circuit including a plurality of instances connected by a plurality of nets, the method comprising: a slope waveform/bump waveform separation step of separating an input waveform including an superposed input bump waveform, which is input to a delay time calculation subject instance selected from the plurality of instances, into an input slope waveform on which the input bump waveform is not superimposed and the input bump waveform; a library reference step of referring to the function of the above-described cell characteristic characterization method to obtain an output slope waveform and an output bump waveform of the delay time calculation subject instance which correspond to the input slope waveform and the input bump waveform and obtain as an output waveform of the delay time calculation subject instance an output waveform formed by the output slope waveform and the output bump waveform superimposed thereon; and if a bump waveform occurs due to an external factor in a subsequent net connected to an output side of the delay time calculation subject instance, a net waveform calculation step of inputting information of the bump waveform and superimposing the bump waveform on an output waveform of the delay time calculation subject instance to calculate an output waveform of the subsequent net.
Still another aspect of the present invention is directed to an input waveform calculation method for calculating a distorted input signal waveform of a cell which is distorted due to the Miller effect using the above-described cell characteristic characterization method, an input side of the cell being connected to a line, an output side of the cell being connected to a drive load, the method comprising: an input terminal capacitance calculation step of referring to the function of the above-described cell characteristic characterization method to calculate an effective input terminal capacitance which corresponds to an input waveform of the waveform calculation subject cell which is obtained before the distortion and a value of the drive load; and a waveform calculation step of calculating an input waveform of the waveform calculation subject cell which is obtained after the distortion based on an output signal waveform of the line connected to the input side of the input waveform calculation subject cell and a load capacitance obtained by adding the capacitance of the line connected to the input side of the waveform calculation subject cell to the calculated effective input terminal capacitance.
Still another aspect of the present invention is directed to a delay time calculation method for calculating a delay time of a semiconductor integrated circuit with consideration for a waveform distortion, the semiconductor integrated circuit including a plurality of instances connected by a plurality of nets, the method comprising: a delay time calculation step which includes calculating a delay time of all the instances and a line delay time of all the nets, signal waveforms at input and output terminals of all the instances, and an effective input terminal capacitance of all the instances, inputting a Miller effect-causing condition which includes an input signal waveform and an effective input terminal capacitance, collating the input signal waveform and the effective input terminal capacitance calculated for each instance with the Miller effect-causing condition, listing an instance in which the Miller effect is caused in an input signal to output the list as a Miller effect-caused instance list; a static timing analysis step which includes assigning the delay time calculated at the delay time calculation step to a netlist to perform a static timing analysis, determining whether or not a timing of each path satisfies a timing design specification, if the timing design specification is not satisfied, storing a difference between a timing of the unsatisfactory path and the timing design specification as slack information; a Miller effect-caused instance extraction step which includes collating an instance included in a path which is determined not to satisfy the timing design specification at the static timing analysis step with the Miller effect-caused instance list, if the instance included in the path is included in the Miller effect-caused instance list, calculating a delay variation caused due to the Miller effect of the instance to output the calculated delay variation as a path delay variation report; and a timing redetermination step which includes collating the slack information of the path which is determined not to satisfy the timing design specification with the path delay variation report, and if the timing design specification is satisfied with the delay variation caused due to the Miller effect, redetermining that the path satisfies the timing design specification.
Still another aspect of the present invention is directed to a delay time calculation method for calculating a delay time of a semiconductor integrated circuit with consideration for a waveform distortion, the semiconductor integrated circuit including a plurality of instances connected by a plurality of nets, the method comprising: a static timing analysis step which includes inputting a netlist, a delay time of the plurality of instances, and a line delay time of the plurality of nets, and assigning the delay time and the line delay time to the netlist to perform a static timing analysis; a timing MET determination step of determining whether or not a result of the timing analysis at the static timing analysis step satisfies a timing design specification; if it is determined at the timing MET determination step that the timing design specification is not satisfied, a circuit modification step of performing a circuit modification including change of the instance size or rearrangement of lines based on layout information for timing correction; a delay time calculation step which includes calculating a delay time of all the instances and a line delay time of all the nets after the circuit modification of the circuit modification step, and after the calculation, returning to the static timing analysis step; if it is determined at the timing MET determination step that the timing design specification is satisfied, a Miller effect-caused instance extraction step of extracting an instance included in a path in which the Miller effect occurs based on a Miller effect-causing condition but the timing fails to satisfy the timing design specification as a result of the occurrence of the Miller effect; and a circuit modification method determination step which includes determining a circuit modification method from a method for modifying the Miller effect-caused instance extracted at the Miller effect-caused instance extraction step and a method for modifying an instance which is a factor that causes the Miller effect, and returning to the circuit modification step.
In one embodiment of the present invention, the circuit modification method determination step includes: a Miller effect-caused instance modification method presentation step of presenting a circuit modification method for changing a cell size of an instance in which the Miller effect is caused to a cell size such that the Miller effect is removed; a Miller effect-causing factor instance modification method presentation step of presenting a circuit modification method for changing a cell size of an instance which generates a signal waveform that causes the Miller effect to a cell size such that the Miller effect is removed; and an optimum modification method selection step of comparing the two circuit modification methods presented at the two modification method presentation steps to select therefrom a circuit modification method which causes minimum area damage.
With the above features of the present invention, an effective input terminal capacitance which is a load replaceable with and effectively equivalent to a cell and a drive load and which represents a load corresponding to a case where a waveform distortion is caused due to the Miller effect is calculated according to the cell characteristics, and the calculated effective input terminal capacitance is characterized while being associated with an input waveform and the drive load.
According to the present invention, an input slope waveform and an input bump waveform are generated, and the input bump waveform is superimposed on the input slope waveform to obtain a bump-superimposed input slope waveform. Then, an output waveform derived from the bump-superimposed input slope waveform is separated into an output slope waveform and an output bump waveform. The input and output bump waveforms are defined by parameters which are represented by a waveform transition time, a bump waveform height, a bump waveform width, a bump area, a time interval which elapses till the bump reaches a peak, and a timing at which the bump waveform is superimposed on the waveform. The input and output slope waveforms on which the input and output bump waveforms are superimposed are associated with the input slope waveform on which the bump waveform is not superimposed and the drive load corresponding to a case where the bump occurs, whereby the cell characteristics are characterized.
According to the present invention, a cell having a small driving capacity is connected to the input side of a cell characteristics characterization subject cell. With such a feature, an input waveform distortion of the cell characteristics characterization subject cell is acutely sensed. The condition which causes a waveform distortion is converted into a two-dimensional table of the input transition value of an input slope waveform in which a distortion is not caused and a drive load capacitance value corresponding to a case where a distortion is caused, whereby the cell characteristics are characterized, and a result thereof is converted to a library.
According to the present invention, the drive load capacitance driven by a cell and the input transition value to the cell are detected, and a library is referred to as to the detected parameters to extract a pattern which generates a distortion in a waveform based on the drive load capacitance value and the input transition value. If a distortion-generating pattern is not extracted, a gate-level delay time calculation is performed, whereby the process time is shortened. If a distortion-generating pattern is extracted, a transistor-level delay time calculation is performed. In the transistor-level delay time calculation, it is detected whether or not a distortion is caused in an output waveform. After a distortion is not caused in the output waveform, another delay time calculation subject is then processed.
According to the present invention, the delay time of all the instances and lines in a design and the signal waveforms at input and output terminals are calculated based on a delay library and RC information. The variable capacitance value is represented as a coupling capacitance between the input and output terminals of a cell, whereby the Miller effect is considered. In addition to a variation of the input waveform due to the Miller effect, a crosstalk calculation is performed with a net connected to the output terminal of an instance as an aggressor and a net connected to the input terminal of the instance as a victim, whereby a signal waveform transfer between the input and output terminals of the instance is calculated, and an instance output signal waveform is calculated with consideration for the Miller effect. Then, a delay time of a cell is calculated from the thus-obtained instance input signal waveform and instance output signal waveform. Further, each of the signal waveforms is allowed to transfer, and the line delay and the delay time of other cells are calculated. In this way, a variation of a signal waveform and a delay time variation due to the Miller effect can be calculated.
According to the present invention, also in obtaining an output waveform of the instance, an output waveform of an instance is calculated with consideration for the Miller effect from the variable capacitance value due to the Miller effect and the waveforms at the input and output terminals as in obtaining the input waveform. Furthermore, a crosstalk calculation is performed with a net connected to the instance input terminal as an aggressor and a net connected to the instance output terminal as a victim, whereby a variation of an instance output signal waveform is calculated with consideration for the Miller effect and the crosstalk.
According to the present invention, a net waveform is separated into a bump waveform and a net input slope waveform, and the obtained library is referred to to obtain a net output waveform including a superimposed bump waveform. If a bump waveform is caused due to an external factor, such as crosstalk, simultaneous transition noise, overshoot or undershoot due to inductance, or the like, the bump waveform caused due to such an external factor is also superimposed on the net waveform to obtain a net output waveform.
According to the present invention, a circuit portion which includes a net subsequent to an instance subjected to a delay time calculation (delay time calculation subject instance) and the input terminal capacitance of an instance subsequent to the net that is subsequent to the delay time calculation subject instance falls back into an effective drive load of the delay time calculation subject instance. The library obtained by the delay time calculation subject circuit characterization method is referred to as to the drive load and the input terminal capacitance of the instance in which the Miller effect is not caused to obtain an equivalent input terminal capacitance. Further, the library is referred to to obtain an effective input terminal capacitance which replaces the equivalent input terminal capacitance and the drive load. Then, a waveform calculation is performed using the effective input terminal capacitance, whereby the cell delay and the cell output slew rate are calculated.
According to the present invention, a list of instances in which the Miller effect is caused is prepared based on the input waveform and the drive load capacitance to be driven, along with the delay time calculation of all the instances and the line delay time calculation. As for a path which fails to satisfy a static timing, an instance in which the Miller effect is caused is extracted from the instances of the list. Herein, the timing redetermination is performed with consideration for the static timing and the delay caused by the Miller effect.
Further, according to the present invention, if the timing specification is not satisfied as a result of a static timing analysis, the delay time calculation process of the present invention proceeds to a circuit modification step. If the timing specification is satisfied, the presence/absence of occurrence of the Miller effect is verified. At this step, if the Miller effect does not occur, the delay time calculation is terminated. If the timing specification is not satisfied due to occurrence of the Miller effect, a circuit modification method is determined, and the delay time calculation process of the present invention proceeds to the circuit modification step. After the circuit modification step, a delay time calculation is carried out to perform a static timing analysis again.
According to the present invention, in the determination of a circuit modification method in the delay time calculation method, a method for modifying an instance in which the Miller effect occurs and a method for modifying an instance which influences occurrence of the Miller effect are compared, and one of the methods which causes the minimum area damage is selected.
Hereinafter, preferred embodiments of the present invention are described with reference to the attached drawings.
Embodiment 1 of the present invention is described with reference to
Herein, in the process of calculating the effective input terminal capacitance 1205, the equivalent input terminal capacitance is first calculated, and then, the effective input terminal capacitance 1205 is calculated using the equivalent input terminal capacitance. Specifically, in the case where the load section 1203 of
Herein, the process flow of
In
At the circuit simulation step 1102, a circuit simulation is carried out based on the simulation script generated at step 1101. It should be noted that, as for the input waveform of this circuit simulation, the input slew rate value is changed by adjusting the parameters of the waveform generation circuit 1201 and the smoothing circuit 1202 shown in
At the effective input terminal capacitance calculation step 1103, when the waveform input to the characterization subject cell 1204 is not the waveform 1210 which is free from the Miller effect but the waveform 1211 which results from the Miller effect as shown in
At the circuit simulation step 1104, a circuit simulation is carried out using a circuit diagram shown in
As for the result of the circuit simulation at the circuit simulation step 1104, the delay at the drive point on the input waveform is compared with the delay of the waveform 1211 which results from the Miller effect. The series of steps 1103 and 1104 is repeated till the delay at the drive point becomes equal to or smaller than a predetermined threshold.
The effective input terminal capacitance 1205 calculated at step 1103 and the equivalent input terminal capacitance are recorded and stored in table data 1115 (storage step) as a function of the slew rate of the input waveform 1210 and the load section 1203 which are obtained when the Miller effect is not caused, together with the previously-obtained result of the circuit simulation step 1102.
The series of steps 1101 to 1104 is repeated till all of the patterns described in the measurement condition data 1113 are characterized.
It should be noted that, although only the rising edge is described herein, table data of the effective input terminal capacitance, the cell output slew rate value and the cell delay value is also generated as to a falling edge through the same process.
In the example of embodiment 1, the function is in the form of table data, but the present invention is not limited thereto. For example, the function may be represented by a polynomial.
As described above, according to embodiment 1, even when waveform distortion is caused due to the Miller effect, the influence of the waveform distortion is modeled by the variation of the equivalent input terminal capacitance, and the characteristics of a cell (delay time calculation subject circuit) can be characterized with high accuracy by using the model.
Further, logic synthesis can be carried out with the worst delay value by using the library described in embodiment 1. That is, return steps which occur after a layout process can be reduced.
Next, embodiment 2 of the present invention is described with reference to
Herein, the flowchart of
In
At the circuit simulation step 1302, a circuit simulation is carried out based on the simulation script generated at step 1301. Now, consider a case where the waveform on which the bump is superimposed as shown in
At the waveform/bump separation step 1303, assuming that the waveform shown in
As described above, the cell characteristics of the characterization subject cell 1404, i.e., the output waveform characteristics of the characterization subject cell 1404 which are obtained when the waveform 1405 defined by the input slope waveform 1406 and the bump waveform 1407 superimposed thereon as shown in
The series of steps 1301 to 1303 is repeated till all of the patterns described in the measurement condition data 1313 are characterized.
As described above, according to embodiment 2, a cell can be characterized even if a waveform of a non-monotonous increase or decrease has a distortion.
Embodiment 3 of the present invention is described with reference to
At step ST201 of
At step ST202, the script and circuit connection information generated at step ST201 are read in, and cell characterization is carried out. Herein, the cell which is subjected to the characterization is the characterization subject cell C1 of
As a result of the characterization at step ST202, an input waveform D201 is output as output data which corresponds to the waveform C5 input to the characterization subject cell C1 of
At the waveform distortion detection (waveform distortion observation) step ST203, a waveform distortion of the input/output waveforms of the characterization subject cell C1 is detected based on the input waveform D201 and the output waveform D202.
The three pieces of information obtained at steps ST202 and ST203, i.e., the presence/absence of waveform distortion, the delay value D203 of the characterization subject cell C1, and the output transition D204 of the characterization subject cell C1, are subjected to the process of the next step ST204. Specifically, at step ST204, a table in which the aforementioned three pieces of information (the presence/absence of waveform distortion, the delay value D203, and the output transition D204) are written with the input slope waveform C5 and drive load C3 of the characterization subject cell C1 as indices is prepared and stored as table data L201 for a library.
It should be noted that, when waveform distortion is not detected, the delay value D203 and the output transition D204 which are obtained at step ST202 can be used for a general delay time calculation. Even when a waveform distortion is detected, the delay value D203 and the output transition D204 can be used as a delay value and slope obtained on the occurrence of a waveform distortion so long as the waveform distortion causes no influence on the measurement of the delay value and slope and is permissible in view of accuracy. However, in a delay time calculation carried out with high accuracy, the delay value D203 and the output transition D204 should not be used if they are obtained when a waveform distortion occurs.
Embodiment 4 of the present invention is described with reference to
In
If there is a cell which is to be subjected to the delay time calculation (“YES” at step ST40), the input transition value and the drive load capacitance of the delay time calculation subject cell are calculated (drive load/input waveform extraction step ST41).
At the distortion-generating pattern detection step ST42, it is determined from the input transition value and drive load calculated at step ST41 whether or not there is a pattern of a cell which generates a distortion in the waveform. In the determination at step ST42, the library L201 in which one or more patterns that generate waveform distortion are registered (as obtained in embodiment 3) is referred to. (It should be noted that the library is shown as “library L40” in
At the waveform distortion detection step ST44, the output waveform obtained as a result of the transistor-level delay time calculation at step ST43 is referred to. If the waveform has a distortion (“YES” at step ST44), the process returns to step ST43. At step ST43, the transistor-level delay time calculation is carried out again. If the waveform has no distortion (“NO” at step ST44), the process returns to step ST40. At step ST40, the delay time calculation is performed on another delay time calculation subject cell.
At step ST45, a gate-level delay time calculation is performed on a pattern which generates no distortion using a general library L41 which is written as the function of the transition value input to the cell and the drive load. The calculation result is stored as the delay information D40 in the database as is the result of the transistor-level delay time calculation of step ST43. Then, the process returns to step ST40, and a next delay time calculation subject cell is searched for.
Embodiment 5 of the present invention is described with reference to
Herein, the flowchart of
In
In this calculation with the circuit structure shown in
At the instance input signal waveform calculation step SX101, the signal waveforms input to the instances, which vary due to the Miller effect, are recalculated using a variable capacitance value X100 that describes the variation of the terminal capacitance which varies due to the Miller effect in each cell and the input/output signal waveforms X101. At step SX101, the recalculation is carried out with the coupling capacitance X205 added between the input and output terminals of the instance X201 of
Furthermore, at step SX101, the influence of a signal variation at the output terminal of the instance X201 on the line X204 is calculated. In the meantime, a crosstalk calculation of the output-side line X204 of the instance X201 with respect to the input-side line X203 of the instance X201 is carried out with the line X204 as an aggressor and the line X203 as a victim. As a result, an input signal waveform X213 of the instance X201 shown in
At the instance output signal waveform transfer step SX102, an output signal waveform X214 to be transferred of the instance X201 is calculated from the signal waveform X213 input to the instance X201 and RC information of the line X204 with consideration for the Miller effect as shown in
At the second delay time calculation step SX103, the output signal waveform X103 obtained at the instance output signal waveform transfer step SX102, in which the Miller effect is considered, is used to perform the delay time calculation again on all of the instances and lines. Specifically, the Miller effect-considered input signal waveform X102 obtained at step SX101 and the Miller effect-considered output signal waveform X103 obtained at step SX102 are used. The time interval between the threshold voltages of the waveforms X102 and X103 is assumed as a delay time. As shown in
As described above, a bump is generated by expressing the variation of the input terminal capacitance of an instance as a coupling capacitance, whereby a variation of a signal waveform which is caused due to the Miller effect is expressed.
According to the method described in embodiment 5, delay time calculation and timing analysis can be carried out with consideration for the signal waveform and delay time which vary due to the Miller effect. Thus, a timing error caused by the Miller effect can be avoided.
Especially in a gate which has a structure where a signal passes through only one transistor gate between the inlet and outlet of the gate (e.g., an inverter, NAND, NOR, or the like), a waveform blunted at the input terminal of the gate is likely to influence the output of the gate. Thus, the delay time calculation can be carried out with high accuracy by using the method of embodiment 5 of the present invention.
Embodiment 6 of the present invention is described with reference to
The instance output signal waveform calculation step SX300 of embodiment 6 is different from the instance output signal waveform transfer step SX102 of embodiment 5 in that the variable capacitance value X100 is used as an input value.
The flowchart of
In
In this calculation with the circuit structure shown in
At the instance input signal waveform calculation step SX101, the signal waveforms input to the instances, which vary due to the Miller effect, are recalculated using a variable capacitance value X100 that describes the variation of the terminal capacitance which varies due to the Miller effect in each cell and the input/output signal waveforms X101. At step SX101, the recalculation is carried out with the coupling capacitance X205 added between the input and output terminals of the instance X201 of
Furthermore, at step SX101, the influence of a signal variation at the output terminal of the instance X201 on the line X204 is calculated. In the meantime, a crosstalk calculation is carried out with the line X204 as an aggressor and the line X203 as a victim. As a result, an input signal waveform X213 of the instance X201 shown in
At the instance output signal waveform calculation step SX300, an output signal waveform X400 of the instance X201 is calculated from the variable capacitance value X100 that describes the variation of the terminal capacitance which varies due to the Miller effect in each cell and the input/output signal waveforms X101 of the instance X201 (the input signal waveform X207 and the output signal waveform X208 of
In the recalculation of the output signal waveform of the instance X201 at step SX300, for representation of the output signal waveform with consideration for the Miller effect, the influence of a signal variation at the input terminal of the instance X201 of
At the second delay time calculation step SX103, the output signal waveform data X103 obtained at the instance output signal waveform calculation step SX300, in which the Miller effect is considered, is used to perform the delay time calculation again on all of the instances and lines. According to this delay recalculation method, a calculation is carried out while the signal waveform calculated in the above process is assumed as the time interval between their threshold voltages. As shown in
As described above, a bump is generated by expressing the variation of the input terminal capacitance of an instance as a coupling capacitance, whereby a variation of a signal waveform which is caused due to the Miller effect is expressed.
According to the method described in embodiment 6, delay time calculation and timing analysis can be carried out with consideration for the signal waveform and delay time which vary due to the Miller effect. Thus, a timing error caused by the Miller effect can be avoided.
Especially in a gate which has a structure where a signal passes through a plurality of transistor gates (e.g., a buffer, AND, OR, or the like), a waveform blunted at the input terminal of the gate is unlikely to influence the output of the gate. Thus, in such a case, even when the method described in embodiment 6 (i.e., a method which uses the capacitance value variable due to the Miller effect even in the process of obtaining an instance output signal waveform as in the process of obtaining an instance input signal waveform) is used in place of the method described in embodiment 5, the delay time calculation can be carried out with high accuracy.
Embodiment 7 of the present invention is described with reference to
The flowchart of
Referring to
At the net waveform separation step (input slope waveform/bump waveform separation step) 2102, a waveform input to Instance_12120 described in waveform information 2114, which includes a superimposed bump, is divided into an input slope waveform 2131 and a bump waveform 2132 shown in
At the network fallback step 2103, a circuit which is formed by Net_12126 and the input terminal capacitance of Instance_22121 at the next stage falls back based on parasitic element information 2111. In this step, the drive load of Instance_12120 is obtained.
At the library reference step 2104, a library 2112 which is prepared based on the cell characteristic characterization method described in embodiment 2 when a bump waveform is superimposed on a waveform (corresponding to the table data 1315 of
At the net waveform calculation step 2105, waveform analysis is carried out based on the output waveform of Instance_12120 which is obtained at the library reference step 2104. In this analysis, the line delay value of Net_12126 and the input waveform of Instance_22121 are calculated. The line delay value of Net_12126 is recorded in the delay information 2115, and the input waveform of Instance_22121 is recorded in waveform information 2114.
Next, it is assumed that, at the network selection step 2101, the second network of
At the net waveform separation step 2102, the waveform input to Instance_22121 described in the waveform information 2114, which includes a superimposed bump, is separated into an input slope waveform and a bump waveform.
At the network fallback step 2103, a circuit which is formed by Net_22127 and the input terminal capacitance of Instance_32122 at the next stage falls back based on the parasitic element information 2111. In this step, the drive load of Instance_22121 is obtained.
At the library reference step 2104, the library 2112 is used to obtain a cell delay and an output waveform which is represented by a waveform including a superimposed bump waveform. The cell delay is recorded in delay information 2115.
As for Net_22127, Net_A12128 which has a coupling capacitance exists in the vicinity of Net_22127, and accordingly, interline crosstalk occurs therebetween. The interline crosstalk causes an external bump waveform 2133. The external bump waveform 2133 is calculated through another process and described in external bump waveform information 2113. Thus, at the net waveform calculation step 2105, waveform analysis is carried out using a waveform which is formed by the output waveform of Instance_22121 obtained at the library reference step 2104 and the external bump waveform 2133 superimposed thereon, whereby the line delay value of Net_22127 and the input waveform of Instance_32122 are calculated. The line delay value of Net_22127 is recorded in the delay information 2115, and the input waveform of Instance_32122 is recorded in the waveform information 2114.
It should be noted that superimposition of the external bump waveform may be determined in consideration of the transition timing of Net_A12128 and the transition timing of Net_22127. For example, when Net_A12128 and Net_22127 do not transition at the same time, the external bump waveform may not be superimposed.
In the example of embodiment 7, the cause of the external bump waveform is crosstalk. However, the cause may be simultaneous switching noise, overshoot or undershoot due to inductance, or the like.
This series of steps for delay time calculation is repeated till the delay time calculation is performed on all of the nets described in the netlist 2110.
As described above, according to embodiment 7, even when waveform distortion is caused by crosstalk, simultaneous switching (simultaneous transition) noise, overshoot or undershoot due to inductance, or the like, delay time calculation can be performed with high accuracy with consideration for the influence of the waveform distortion.
Embodiment 8 of the present invention is described with reference to
The flowchart of
Referring to
At the default input terminal capacitance reference step 2204, as for an instance connected between the net which is a subject of delay time calculation and the subsequent net, a library 2212 in which the input terminal capacitance is characterized as the function of the input slew rate and the drive load according to the characterization method described in embodiment 1 is referred to, and the input terminal capacitance which is obtained when the Miller effect is not caused is extracted. In the example of
At the net waveform calculation step (first net waveform calculation step) 2205, the library 2212 is referred to using the output slew rate of a net previous to Net_12226, i.e., the input slew rate of Instance_12220, which is obtained from waveform information 2214, and the pre-variation input terminal capacitance (load section) of the network circuit which has fallen back at step 2203 (i.e., a circuit formed by Net_12226 and Instance_22221) as indices to calculate the cell output slew rate of Instance_12220. Furthermore, the waveform 2231 obtained before a variation of the effective input terminal capacitance, which is the output slew rate of Net_12226, is calculated by waveform analysis.
At the input terminal capacitance calculation step 2206, the library 2212 is referred to using the slew rate of the waveform 2231 which is obtained before a variation of the effective input terminal capacitance of Instance_22221 (i.e., obtained when the input waveform includes no distortion) and the load capacitance of Net_22227 which has fallen back at step 2203 as indices to calculate the post-variation effective input terminal capacitance of Instance_22221.
At the network fallback step (second network fallback step) 2207, a circuit formed by a net which is a subject of delay time calculation and the post-variation effective input terminal capacitance of an instance at the next stage which is connected to the net falls back. In the example described herein, a circuit formed by Net_12226 and the post-variation effective input terminal capacitance of Instance_22221, which has been calculated previously, falls back.
At the net waveform calculation step (second net waveform calculation step) 2208, the library 2212 is referred to using the output slew rate of a net previous to Net_12226 (i.e., the input slew rate of Instance_12220), which is obtained from waveform information 2214, and the load section which has fallen back (i.e., a circuit obtained as a result of the fallback of the circuit formed by Net_12226 and the post-variation effective input terminal capacitance of Instance_22221) as indices to calculate the cell delay value and cell output slew rate of Instance_12220. The cell delay value and the cell output slew rate of Instance_12220 are recorded in the waveform information 2214 and the delay information 2215, respectively. Furthermore, a waveform 2232 obtained after a variation of the effective input terminal capacitance, which is the output slew rate of Net_12226, and the line delay time of Net_12226 are calculated by waveform analysis and recorded in the waveform information 2214 and the delay information 2215, respectively.
A series of steps for the above-described delay time calculation is repeated till the delay time calculation is performed on all of the nets described in the netlist 2210.
As described above, according to embodiment 8, even when waveform distortion is caused due to the Miller effect, the delay time calculation can be performed with high accuracy in consideration of the influence of the waveform distortion in consideration of the influence of the waveform distortion by using a model of the variation of the effective input terminal capacitance.
Embodiment 9 of the present invention is described with reference to
The method of
The flowchart of
In the delay time calculation step SX500, the delay time and line delay time of all the instances in a design are calculated based on the delay library X104 and RC information X105. In the meantime, it is determined, for each instance, from the input signal waveform slope of the instance and a load capacitance to be driven according to the Miller effect-causing condition X505 whether or not the Miller effect is caused. Then, the instance(s) in which the Miller effect is caused is output as the Miller effect-caused instance list X501. The Miller effect-causing condition X505, which is used at the delay time calculation step SX500, describes the input signal waveform slope and the capacitance value for each cell type. As for each cell, if an input signal waveform has a slope larger than the input signal waveform slope and there is an instance which drives a capacitance smaller than the capacitance value, it is determined that the Miller effect is caused in the cell.
It should be noted that, in the example of embodiment 9, the delay library X104 and the RC information X105 are read in at the delay time calculation step SX500. However, a netlist of a design, setting of a boundary and/or timing restrictions may be additionally read in for delay time calculation. In this specification, the “cell” means a logic-level element, such as a buffer, an inverter, or the like, and the “instance” is only a name for distinguishing a plurality of cells of the same type.
Then, at the static timing analysis step SX501, the delay value of the delay information X500 is assigned to the netlist X506 to carry out a timing analysis.
If in the timing analysis there is a path which fails to satisfy the timing, the path report X502 which describes a list of instances that constitute the path and the slack information X503 which describes the unsatisfied time for the timing the path has to keep are output.
For example, assuming that the path found at step SX501 is a path which extends from the flip flop X600 to the flip flop X601 through the instance X602 as described in
Further, assuming that the specification the delay of the path has to satisfy is, for example, the hold time X604 as shown in
Then, at the Miller effect-caused instance extraction step SX502, it is determined whether or not an instance described in the Miller effect-caused instance list X501 is included in the path report X502. If included, the delay variation caused by the Miller effect in the instance is output as the path delay variation report X504.
For example, assuming that the instance X602 is included in the Miller effect-caused instance list X501, it is determined that the Miller effect is caused in the path between the flip flops X600 and X601, and the delay variation X606 caused by the Miller effect in the instance X602 is calculated.
The method used herein for calculating the delay variation caused by the Miller effect may be the method described in embodiment 3 or 4. Alternatively, the delay variation may be calculated using a circuit simulator.
Lastly, at the timing redetermination step SX503, the slack information X503 and the path delay variation report X504 are compared. A path for which the value described in the slack information X503 is larger than the value described in the path delay variation report X504 is determined to satisfy the timing.
Further, the difference X607 and the delay variation X606 are compared. If the delay variation X606 is larger than the difference X607, the path fails to satisfy the timing. However, when an increase in the delay due to the Miller effect is considered, the path satisfies the timing. Thus, in such a case, it is determined that the path satisfies the timing.
As described above, according to embodiment 9, a path which fails to satisfy the timing as it is but satisfies the timing when an in crease in the delay occurs due to the Miller effect is determined not to have to be subjected to circuit modification. Thus, it is not necessary to make an additional circuit modification. Accordingly, the number of steps can be reduced, and an increase in area can be suppressed.
Embodiment 10 of the present invention is described with reference to
The method of
The process of
The flowchart of
Firstly, at the static timing analysis step SX700, the delay information X500 is assigned to the netlist X506, and a static timing analysis is carried out.
Then, at the timing MET determination step SX701, it is determined whether or not the timing satisfies the specification as a result of the static timing analysis. If the timing is not satisfied (“NO” at step SX701), the process proceeds to the circuit modification step SX702.
At the circuit modification step SX702, the layout X700 is read in, and change of the cell size, rearrangement of lines, or the like, is carried out, whereby the timing is corrected.
Then, at the delay time calculation step SX703, the delay time of all the instances and lines in the timing-corrected design is calculated, and the process returns to the static timing analysis step SX700. The above steps are repeated till the timing satisfies the specification.
If the timing satisfies the specification at the timing MET determination step SX701, the process proceeds to the Miller effect-caused instance extraction step SX704.
At the Miller effect-caused instance extraction step SX704, when instances which constitute a path having a timing error meet the Miller effect-causing condition X505, the instances are extracted.
Then, at the Miller effect determination step SX705, it is determined whether or not the instances extracted at the Miller effect-caused instance extraction step SX704 include an instance in which the Miller effect is caused. If there is such an instance (“YES” at step SX705), it is determined that a circuit modification is necessary. Then, at the circuit modification method selection step SX706, a circuit modification method is selected, and the process proceeds to the circuit modification step SX702. If there is not an instance in which the Miller effect is caused (“NO” at step SX705), it is determined that the timing correction has been completed, and the process is terminated.
The circuit modification method selection step SX706 of the above process is now described in detail using the flowchart of
The circuit modification method selection step SX706 includes the Miller effect-caused instance modification method presentation step SX800, the Miller effect-causing factor instance modification method presentation step SX801, and the optimum modification method selection step SX802 as shown in
In the circuit of
Since the Miller effect is caused by a signal waveform input to the instance and the load capacitance, it is then determined whether or not the modification can be realized by changing the signal waveform input to the instance X900 or the load capacitance.
At the Miller effect-causing factor instance modification method presentation step SX801, a method for changing the cell size of the instance X901 to change the signal waveform input to the instance X900 in which the Miller effect is caused is presented. In the change of cell size by the presented method, in general, the cell size of the instance X901 is increased (i.e., the driving capacity is improved) to the size of the instance X904 as shown in
At the optimum modification method selection step SX802, the increase in area due to the change of cell size is compared between the instance X903 and the instance X904, and one of the methods presented at step SX800 and step SX801 which causes the smaller area damage is selected.
At the circuit modification step SX702, the circuit layout is modified using the method selected at step SX802.
As described above, at the occasion of timing correction, it is determined whether or not there is an instance in which a delay variation occurs due to the Miller effect, and the circuit modification method which causes the minimum area damage is presented. Thus, the Miller effect is avoided with the minimum damage, and teething troubles at the market can be prevented before they happen.
Number | Date | Country | Kind |
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2004-123450 | Apr 2004 | JP | national |