Claims
- 1. A method of predicting the SEU susceptibility of a SRAM; the method comprising the steps of:
- a) providing an enhanced SEU sensitivity test SRAM having an electrically adjustable critical charge;
- b) determining the critical charge as a function of offset voltage to ascertain the upset capacitance C.sub.US of said test SRAM;
- c) exposing the test SRAM to a first known level of alpha particle energy to ascertain the overlayer thickness of said SRAM, said first known level being selected to stop the alpha particle energy in the collection layer of said SRAM;
- d) calculating the overlayer thickness .delta.X.sub.3 of said test SRAM based upon the charge deposited by said first known level;
- e) exposing the test SRAM to a second known level of alpha particle energy to ascertain the charge collection thickness of said SRAM, said second known level being selected so alpha particle energy stops beyond the collection layer;
- f) calculating the collection layer thickness .delta.X.sub.4 of said test SRAM based upon charge deposited by said second known level and the calculated thickness of said overlayer; and
- g) calculating the linear energy transfer (LET) for said test SRAM: ##EQU7## where V.sub.op.mu. =the peak value of offset voltage at maximum particle upset distribution;
- V.sub.os.mu. =the mean offset voltage in the spontaneous flip range;
- K=the hole-election pair charge-energy factor for silicon;
- .rho.=the density of silicon;
- C.sub.US =upset capacitance for SRAM.
- 2. The method recited in claim 1 wherein in step a) said SRAM is made more sensitive to incident-ion-induced SEU by providing at least one pull-down field effect transistor having a bloated drain surface area and at least one pull-up field effect transistor having a source connected to an offset voltage.
- 3. The method recited in claim 1 wherein said offset voltage is determined by measuring the offset voltage at which about one-half of the total number of latch cells are upset spontaneously without deliberate ion exposure.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is a continuation-in-part of U.S. patent application Ser. No. 07/672,705, filed on Mar. 19, 1991, now U.S. Pat. No. 5,331,164.
ORIGIN OF INVENTION
The invention described herein was made in the performance of work under a NASA Contract, and is subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected to retain title.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
4529884 |
Wolicki et al. |
Jul 1985 |
|
Non-Patent Literature Citations (1)
Entry |
Zoutendyk et al., "Empirical Modelling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips." IEEE Transactions on Nuclear Science, vol. NS-33, No. 6, pp. 1581-1585, Dec. 1986. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
672705 |
Mar 1991 |
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