Claims
- 1. A system comprising:
- an encoder for encoding input data as a first bitstream; and
- a processor for receiving as input the first bitstream and for generating as an output a second bitstream by inserting padding bits into the first bitstream so that said second bitstream is comprised of equal length bit sequences, each of said equal length bit sequences being developed from a respective portion of said first bitstream;
- wherein each of the equal length bit sequences is an independently decodeable clip comprising a sequence of frames, so that a seamless transition is made from said second bitstream to a third bitstream comprised of encoded input data, after completion of one of said equal length bit sequences of said second bitstream, while underflow or overflow as a result of said transition in a decoder buffer of a decoder which is operable to decode a resulting bitstream is avoided.
- 2. The system of claim 1 further comprising an encoder data buffer associated with the encoder wherein the capacity of the encoder data buffer is less than one half the capacity of the decoder buffer.
- 3. The system of claim 1 wherein the encoder and decoder include means for encoding and decoding the input data according to the Motion Picture Experts Group (MPEG) standard, with the decoder buffer having a predetermined fixed capacity.
- 4. The system of claim 1 wherein the padding bits are each the same predetermined logic level.
- 5. The system of claim 1 wherein the processor generates the second bitstream by inserting predetermined bits into the first bitstream such that the second bitstream has a size Rd*T, in which Rd is a desired bit rate and T is the duration of the second bitstream after decoding by the decoder.
- 6. The system of claim 1 wherein said third bitstream is a portion of said second bitstream.
- 7. The system of claim 1 wherein said third bitstream is distinct from said second bitstream.
- 8. The system of claim 1 wherein the encoder encodes the input data at an actual rate R.sub.a such that
- Ra*T+Bf-Bi.ltoreq.Rd*T
- where T is a predetermined length, R.sub.d is a desired decoding rate, and B.sub.i and Bf are the initial and final occupancies of an encoder data buffer.
- 9. The system of claim 8 wherein the encoder encodes the input data at an actual rate R.sub.a such that
- T*(R.sub.d -R.sub.a).ltoreq.B.sub.d -B.sub.e,
- where B.sub.d is the capacity of the decoder buffer, and B.sub.e is the capacity of the encoder data buffer.
- 10. The system of claim 8 wherein the encoder data buffer has a total buffer capacity B.sub.e, wherein
- B.sub.e .ltoreq.T*(R.sub.d -R.sub.a)
- where T is the predetermined length and R.sub.d is a desired decoding rate.
- 11. A system comprising:
- an encoder for encoding input data as a first bit sequence in a first bitstream, said first bit sequence having a length, in number of bits, less than a predetermined length; and
- a processor for receiving as input the first bit sequence of the first bitstream and for generating as an output a second bit sequence which is exactly the predetermined length, a second bitstream being generated by the processor inserting padding bits into the first bitstream;
- wherein said second bit sequence is an independently decodeable clip comprising a sequence of frames so that a transition from said second bitstream to a third bitstream comprised of encoded input data, after completion of said second bit sequence, is seamless and avoids underflow or overflow as a result of said transition in a decoder buffer of a decoder which is operable to decode a resulting bitstream.
- 12. The system of claim 11 wherein said third bitstream is a portion of said second bitstream.
- 13. The system of claim 11 wherein said third bitstream is distinct from said second bitstream.
- 14. The system of claim 11 wherein each of the encoder and the decoder operates according to the Motion Picture Experts Group (MPEG) standard as an MPEG encoder and an MPEG decoder, respectively.
- 15. The system of claim 14 wherein the encoder generates a VBV.sub.-- DLY signal corresponding to the first bit sequence; and
- the processor responds to the generation of the second bit sequence to update the VBV.sub.-- DLY signal to correspond to the second bit sequence.
- 16. A method comprising the steps of:
- receiving input data;
- encoding the input data using an encoder having a data buffer to generate a first bit sequence in a bitstream;
- receiving as input the first bit sequence; and
- selectively inserting padding bits into the first bitstream so as to generate as output a set of modified bit sequences of equal bit sequence lengths in the bitstream for facilitating reordering of the equal length bit sequences, wherein the set of modified bit sequences, assembled in an arbitrary order, are decodeable by a decoder to generate a decoded output signal, whereby seamless switching of different bit sequences is facilitated.
- 17. The method of claim 16 wherein the steps of encoding and decoding include the step of encoding and decoding the input data according to the Motion Picture Experts Group (MPEG) standard.
- 18. The method of claim 16 further comprising the steps of:
- receiving the bitstream; and
- decoding the set of modified bit sequences to generate the decoded output signal free of editing artifacts.
- 19. The method of claim 16 wherein the steps of encoding and decoding include the steps of encoding and decoding input video data, respectively, according to the Motion Picture Experts Group (MPEG) standard using an MPEG encoder and an MPEG decoder, respectively.
- 20. The method of claim 19 wherein the steps of encoding the input video data includes the step of encoding a video clip as the first bit sequence.
- 21. A system comprising:
- an encoder for encoding input data as a first bitstream;
- a processor for receiving as input the first bitstream and for selectively inserting padding bits into the first bitstream so as to generate as output a set of modified bit sequences of equal bit sequence lengths for facilitating reordering of the equal length bit sequences, wherein the set of modified bit sequences, assembled in an arbitrary order, are decodeable by a decoder to generate a decoded output signal, whereby seamless switching of different bit sequences is facilitated.
- 22. The system of claim 21 wherein capacity of an encoder data buffer within said processor is less than one half of a predetermined buffer size.
- 23. The system of claim 21 wherein the encoder includes means for encoding and decoding the input data according to the Motion Picture Experts Group (MPEG) standard.
- 24. The system of claim 21 wherein the padding bits are each the same predetermined logic level.
- 25. The system of claim 24 wherein the predetermined logic level is logical 0.
- 26. The system of claim 21 wherein the encoder encodes the input data at an actual rate R.sub.a such that a final capacity B.sub.f of an encoder data buffer is less than
- T*(R.sub.d -R.sub.a)+B.sub.i,
- where T is a predetermined length, R.sub.d is a predetermined rate, and B.sub.i is an initial capacity of the encoder data buffer.
- 27. The system of claim 26 wherein the encoder encodes the input data at an actual rate R.sub.a such that
- T*(R.sub.d -R.sub.a).ltoreq.B.sub.d -B.sub.e,
- where B.sub.d is a predetermined buffer capacity, and B.sub.e is the capacity of the encoder data buffer.
- 28. The system of claim 26 wherein the encoder data buffer has a total buffer capacity B.sub.e, wherein
- B.sub.e .ltoreq.T*(R.sub.d -R.sub.a)
- where T is the predetermined length and R.sub.d is a predetermined rate.
- 29. A method comprising the steps of:
- receiving input data;
- encoding the input data using an encoder to generate first bit sequences in a first bitstream;
- receiving as input the first bitstream;
- selectively inserting padding bits into the first bitstream so as to generate as output a set of modified bit sequences of equal length in the first bitstream for facilitating reordering of the equal length bit sequences, wherein the set of modified bit sequences, assembled in an arbitrary order, are decodeable by a decoder to generate a decoded output signal, whereby seamless switching of different bit sequences is facilitated; and
- transmitting the bitstream including the modified bit sequences.
- 30. The method of claim 29 wherein the step of encoding includes the step of encoding the input data according to the Motion Picture Experts Group (MPEG) standard.
- 31. The method of claim 29 wherein the steps of encoding the input data includes the step of encoding a video clip as the first bit sequence.
Parent Case Info
This application is a continuation of application Ser. No. 08/327,176, filed on Oct. 21, 1994 now abandoned.
US Referenced Citations (32)
Non-Patent Literature Citations (1)
Entry |
IMPEG Test Model 4, "Coded Representation of Picture and Audio Information", ISO-IEC/JTC1/SC29/EG11, CCITT SG XV, Working Party XV/1, Document AVC-445b, Feb. 1993. |
Continuations (1)
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Number |
Date |
Country |
Parent |
327176 |
Oct 1994 |
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