Dynamic voltage and frequency scaling (DVFS) is an effective power management technique that is to adjust a clock frequency and a supply voltage according to circumstances of workload. The clock frequency and the supply voltage may be increased to allow the processor to operate at higher speed and to have better performance; and the clock frequency and the supply voltage may be decreased for power saving.
Because increasing the clock frequency and the supply voltage will consume more power, and decreasing the clock frequency and the supply voltage may lower the performance, a central challenge for developing DVFS schemes is to balance two competing objectives: maximizing the power saving and ensuring tight fine-grained performance. Conventional DVFS mechanism is controlled by software governor, however, using software governor to execute the DVFS operation may suffer some problems. For example, if the software DVFS governor operates with an aggressive DVFS policy, that is the software DVFS governor adjusts the clock frequency and the supply voltage at high sensitivity, it may induce more software overhead and impact the performance, and generally the performance drop is more serious for the user than the power saving. On the other hand, if the software DVFS governor operates with an non-aggressive DVFS policy, the software DVFS governor will control the clock frequency and the supply voltage to easily go up but difficultly go down, to keep higher DVFS to avoid performance drop, however, it will cause less power saving.
In addition, in the electronic device such as a smart phone, a plurality of processors are built in for complicated operations, however, the DVFS control of these processors are performed individually rather than adopting an overall arrangement, and the power saving and the system performance may not be optimized.
It is therefore an objective of the present invention to provide a fully hardware DVFS controller, which is able to maximize the power saving and ensure tight fine-grained performance, to solve the above-mentioned problems.
According to one embodiment of the present invention, a controller coupled to a plurality of hardware modules is arranged for determining activities of at least two of the hardware modules in real time, and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.
According to another embodiment of the present invention, a method for controlling a plurality of hardware modules comprises: determining activities of at least two of the hardware modules in real time; and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.
According to another embodiment of the present invention, a system comprises a plurality of hardware modules and a dynamic voltage frequency scaling (DVFS) controller. The DVFS controller is coupled to the plurality of hardware modules, and is arranged for determining activities of at least two of the hardware modules in real time, and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Please refer to
The SOC 100 further couples to a power management integrated circuit (PMIC) 140 that is arranged to provide supply voltages to the hardware modules. In addition, in this embodiment the PMIC 140 is position outside the SOC 100, however, the PMIC 140 may be positioned in the SOC 100.
The SOC 100 is used in an electronic device, such as a smart phone, a tablet or any other device having several processors, to control the operations of the electronic device. Besides the hardware (HW) side,
In this embodiment, the centralized DVFS controller 110 is a hardware DVFS controller that may approach fast DVFS operations. The centralized DVFS controller 110 may receive software information from the dynamic power management 152, and receive activities of the CPU 130_1, GPU 130_2, MM 130_3, MD 130_4 and MC 130_5. The centralized DVFS controller 110 is arranged to provide voltage control signal(s) to the PMIC 140 to control/adjust supply voltages of the CPU 130_1, GPU 130_2, MM 130_3, MD 130_4 and MC 130_5, respectively, based on the software information and the activities of the hardware modules; and the centralized DVFS controller 110 is further arranged to provide PLL control signal(s) to the PLLs 120 to control/adjust clock frequencies of the CPU 130_1, GPU 130_2, MM 130_3, MD 130_4 and MC 130_5, respectively, based on these software information and the activities of the hardware modules.
It is noted that the centralized DVFS controller 110 can be implemented by functional circuits, and could act as a microprocessor, or a digital signal processor. Thus, the centralized DVFS controller 110 can operate more automatically without instructed by a host (such as a CPU), and the host can save burden to avoid software overhead/loading. Moreover, by such kind of implementations, the centralized DVFS controller 110 can operate more efficiently without waiting for host instructions.
In addition, the activity of a hardware module comprises a loading and/or a utilization and/or bandwidth of the hardware module, for example the activity of the CPU 130_1 is the loading/utilization of the CPU 130_1, and the activity of the GPU 130_2 is the loading/utilization of the GPU 130_2, and so on. Particularly, in this embodiment, the activities come from signals of the CPU 130_1, GPU 130_2, MM 130_3, MD 130_4 and MC 130_5. That is the centralized DVFS controller 110 directly gets the activities of the CPU 130_1, GPU 130_2, MM 130_3, MD 130_4 and MC 130_5 via the connections (such as wire connection) within the SOC 100, instead of from the software side.
In this embodiment, there is a dedicated channel set between the centralized DVFS controller 110 and the PMIC 140 to reduce response time of voltage switch, and the centralized DVFS controller 110 may send the voltage control signal(s) to the PMIC 140 via the dedicated channel to fast switch the supply voltage(s) of the CPU 130_1, GPU 130_2, MM 130_3, MD 130_4 and/or MC 130_5.
For the tracking control loops 220 shown in
For the DVFS OPP controller 230, the DVFS OPP controller 230 may provide the voltage control signal(s) to the PMIC 140 to control/adjust supply voltages of the hardware modules, respectively, based on the OPPs determined by the tracking control loops 220; and the DVFS OPP controller 230 provides PLL control signal(s) to the PLLs 120 to control/adjust clock frequencies of the hardware modules, respectively, based on the OPPS determined by the tracking control loops 220. In addition, the DVFS OPP controller 230 adopts an adaptive voltage scaling (AVS) technology according to the chip corner condition and the ambient temperature.
For the SW/HW information exchanger 240, the SW/HW information exchanger 240 may provide a history record of the DVFS operation such as a coarse-grained frequency (e.g. an average of the clock frequencies within a long period, such as 30 ms) to the SW side for general SW framework. The SW/HW information exchanger 240 can send an interrupt to the SW side when instantly dramatic DVFS OPP changes; and/or the SW side can periodically get frequency/loading information (such as moving average) by polling.
As show in
In the embodiments shown in
In one embodiment, not a limitation of the present invention, the supply voltage OPP_V and the clock frequency OPP_F may be determined every millisecond (1 ms) or smaller, and the coarse-grained average frequency may be average of the clock frequency within 30 ms.
Step 500: the flow starts.
Step 502: detect activities of at least two of the hardware modules in real time.
Step 504: determine a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.
The centralized DVFS controller 110 shown in
Briefly summarized, in the embodiments of the present invention, a hardware DVFS controller is used to fast control the DVFS OPP of the hardware modules, and the SW overhead can be avoided. In addition, the hardware DVFS controller further manage the supply voltages and clock frequencies of the hardware modules by referring to the conditions of the whole system, that is the DVFS OPP control of each hardware module may be more accurately.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the priority of U.S. Provisional Application No. 62/144,308, filed on Apr. 7, 2015, which is included herein by reference in its entirety.
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/CN2015/092658 | 10/23/2015 | WO | 00 |
Number | Date | Country | |
---|---|---|---|
62144308 | Apr 2015 | US | |
62127349 | Mar 2015 | US |