METHOD FOR CONTROLLING POWER CONSUMPTION AND MULTI-PROCESSOR SYSTEM USING THE SAME

Abstract

A multi-processor system comprises a clock generator, a clock controller, a main processor, a plurality of co-processors and an interrupt control interface. Because the main processor and the co-processors need not work together to deliver the processing result, the multi-processor system may be designed that each processor in the multi-processor system is independently switched to operate at lower clock or power down completely according to the feedback of the hardware performance detection for each processor when the whole system is in active usage. This means on-demand power saving for the multi-processor system, so as to save power greatly.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic block diagram of a multi-processor system according to one embodiment of the present invention.

FIG. 2 is a flow chart of the method for controlling the power consumption according to one embodiment of the present invention.

Claims

1. A multi-processor system, comprising: a clock generator for generating a plurality of clock signals with different speeds;a clock controller for selecting one clock signal from the clock signals as a first clock signal in respond to a corresponding first control signal, and selecting multiple clock signals from the clock signals as a plurality of second clock signals in respond to a corresponding plurality of second control signals;a main processor, using the first clock signal as the operation clock of the main processor, for outputting the first control signal according to the hardware performance of the main processor, wherein the clock controller is disabled when a disable signal outputted from the main processor is active;a plurality of co-processors, using the second clock signals as the operation clocks of the co-processors respectively, for outputting the second control signals according to the hardware performances of the co-processors respectively, wherein each of the co-processors assists the main processor to perform a specific function operation; andan interrupt control interface coupled among the main processor, the co-processors and the clock controller, for receiving an interrupt signal outputted from the main processor, at least one of the co-processors or the clock controller, and performing a corresponding interrupt operation.

2. The multi-processor system as claimed in claim 1, wherein the multi-processor system includes a system-on-chip (SoC).

3. The multi-processor system as claimed in claim 1, wherein the main processor includes a central processor unit (CPU).

4. The multi-processor system as claimed in claim 1, wherein the co-processors form an audio processor and/or a video processor.

5. The multi-processor system as claimed in claim 1, wherein the interrupt control interface comprises: an interrupt controller for receiving the interrupt signal outputted from the main processor, at least one of the co-processors or the clock controller, and performing the corresponding interrupt operation;a message center for transmitting the status of the main processor and at least one of the co-processors;a status register for registering the status of output, input and middle buffers in the multi-processor system; anda timer for counting so as to stop the corresponding interrupt operation.

6. The multi-processor system as claimed in claim 1, further comprising a direct memory access (DMA) control interface for communicating between the co-processors and external data.

7. A method for controlling the power consumption for a multi-processor system with a plurality of co-processors, the method comprising: one of the co-processors is operated at a first speed;the co-processor is switched to be idle when the hardware performance of the co-processor is detected that the task has been completed;the co-processor is switched to operate at a second speed when the hardware performance of the co-processor is detected that part of the task has been completed, wherein the first speed is faster than the second speed;the co-processor is switched to be idle when the co-processor is operated at the second speed and the hardware performance of the co-processor is detected that the task has been completed;the co-processor is switched to operate at the first speed when the co-processor is operated at the second speed and the hardware performance of the co-processor is detected that the task increases; andthe co-processor is switched to operate at the first speed when the co-processor is idle and receives an interrupt signal.

8. The method for controlling the power consumption as claimed in claim 7, wherein the multi-processor system includes a system-on-chip (SoC).

9. The method for controlling the power consumption as claimed in claim 7, wherein the first speed is a full speed, and the second speed is a half speed.