Patent Grant
8259943
This application claims the benefit of Taiwan application Serial No. 96134749, filed Sep. 17, 2007, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a method for decrypting a signal, and more particularly to a method for decrypting a serial transmission signal.
2. Description of the Related Art
The serial transmission technology has been widely adopted between a transmitting terminal and a receiving terminal, and a serial transmission signal therebetween includes a serial data signal and a serial clock signal.
As shown in
Thereafter, in step 230, it is determined whether the received bit is a command bit, an address bit, a data bit or a special bit, and the received bit then is stored to a corresponding position of a register by way of rotation.
If the data byte is, for example, (b12 b11 b10 . . . b1 b0)2=(1 0 1 . . . 1 0)2, the thirteen data bits are sequentially stored to corresponding positions of the register 300 by way of rotation. First, the bit b12 is stored to the memory cell a0. Next, the bit b12 stored to the memory cell a0 is shifted to the memory cell a1 to complete a first rotation operation. Thereafter, the bit b12 stored to the memory cell a1 is shifted to the memory cell a2 to complete a second rotation operation. After twelve rotation operations have been performed, the bit b12(=1) is stored to the memory cell a12. Thereafter, the bit b11(=0) is stored to the memory cell a11 according to eleven rotation commands. Then, the bit b1(=1) is stored to the memory cell a1 according to one rotation command. The bit b0(=0) is finally stored to the memory cell a0.
In step 240, the receiving terminal determines whether the storing operation finishes after each bit is stored. If the storing operation is not finished yet, the procedure goes back to the step 220 to continue reading the subsequent bits. If the storing operation is finished, the procedure enters step 250. In the step 250, the receiving terminal decrypts the byte stored in the register and performs a corresponding process.
The conventional method for decrypting the serial transmission signal has to push the program address to the stack in the step 220 so as to trigger the interrupt service function and jump to the sub-program, and also has to pop the program address from the stack so as to jump back to the main program. Thus, the processor of the receiving terminal needs a lot of system clock cycles to finish the operation of receiving one bit. Therefore, if the number of bits of the serial transmission signal increases and the transmission speed is required to be higher, the calculation loading of the processor of the receiving terminal will get higher and the efficiency of the processor will be reduced. In addition, if the number of bits of the serial transmission signal increases, the number of rotation commands to be performed in the step 230 will also increase so that the calculation loading of the processor thus get higher. Meanwhile, the cost is increased and the power consumption of the processor of the receiving terminal is increased.
The invention is directed to a method for decrypting a serial transmission signal, in which one bit is read in one cycle of a serial clock signal without using an interrupt service function and then stored by an addition operation. Therefore, the serial transmission signal can be rapidly decrypted, the calculation loading of a processor can be decreased, and the power consumption of the processor can be lowered.
According to a first aspect of the present invention, a method for decrypting a serial transmission signal comprises the following steps. First, the serial transmission signal including a serial data signal and a serial clock signal is received. Next, m bits are sequentially read from the serial data signal according to the serial clock signal. Then, values corresponding to the m bits are generated. Afterwards, each of the values is added to a content value of a register by an addition operation to obtain an addition result, and then the content value is replaced with the addition result and the addition result is stored to the register.
According to a second aspect of the present invention, a method for decrypting a serial transmission signal applied to a receiving terminal comprises the following steps. First, the serial transmission signal including a serial data signal and a serial clock signal is received. Next, it is determined whether a logic level of the serial clock signal is equal to a default value. Then, a bit is read from the serial data signal when the logic level of the serial clock signal is equal to the default value. Afterwards, the bit is stored to a register.
The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
The invention provides a method for decrypting a serial transmission signal, in which one bit is read in one cycle of a serial clock signal without using an interrupt service function and then stored to a corresponding position of a register by an addition operation. Therefore, the calculation loading and the power consumption of a receiving terminal can be decreased, the serial transmission signal can be rapidly decrypted, and the cost of the receiving terminal can be decreased.
First, in step 410, the serial transmission signal including a serial data signal and a serial clock signal is received. Then, in step 420, m bits are sequentially read from the serial data signal according to the serial clock signal, wherein m is a positive integer. The m bits may form, for example, an address byte or a data byte. In addition, in the step 420, the receiving terminal can read the bits from the serial data signal, based on timing pulses contained in the serial clock signal, in an edge triggered or level triggered manner.
Next, in step 430, values corresponding to the m bits are sequentially generated, and an addition result is generated by performing an addition operation for the m values and then stored to a register. In two examples, the addition operation is performed for the m values. In the first example, the addition operation is an arithmetic addition (ADD) operation. It is assumed that the m bits of the first field are sequentially bm-1, bm-2 . . . b1 and b0. When bm-1 is equal to logic 1, the value of 2m-1 is added to a content value stored in the register by the arithmetic addition operation. When the values of bm-2 . . . b1 and b0 are equal to the logic 1, the values of 2m-2 . . . , 21 and 20 are respectively added to the content value stored in the register by the arithmetic addition operation.
In addition to adding the values together in the first example, the m bits may also be stored by way of a logic AND operation. In the second example, the addition operation is a logic AND operation. When bm-1 is equal to logic 1, the value of (1 0 0 . . . 0 0)2 is added to a content value stored in the register by the AND addition operation. When the values of the bm-2 . . . b1 and b0 are equal to logic 1, the values of (0 1 0 . . . 0 0)2, (0 0 1 . . . 0 0)2, . . . (0 0 0 . . . 1 0)2 and (0 0 0 . . . 0 1)2 are respectively added to the content value stored in the register by the logic AND operation. Consequently, the m bits can be stored to the register without multiple rotation commands, thereby decreasing the calculation loading of the receiving terminal. In addition, unlike the conventional method, in which the numbers of rotations for different bits are different, the numbers of addition operations according to the present invention for different bits are the same.
Furthermore, in step 440, it is determined whether the m bits have been completely stored. If the bits have not been completely stored, the procedure goes back to the step 420 to continue reading the remaining bits. If the bits have been completely stored, a first acknowledging bit is outputted to a transmitting terminal in step 450.
Next, in step 515, it is determined whether a logic level of the serial clock signal is equal to a default value “1”. Then, in step 520, when the logic level of the serial clock signal is equal to the default value “1”, one bit is read from the serial data signal. The bit is, for example, one bit of an address byte or one bit of a data byte.
In this embodiment, the method is to read one bit from the serial data signal in one serial clock cycle at the receiving terminal without using an interrupt service function. That is, a main program of the receiving terminal has included program codes for reading the data bit from the serial data signal. The main program is executed by a processor of the receiving terminal, for example, and the frequency of a system clock signal of the processor is higher than that of the serial clock signal. Consequently, the main program can directly perform the operation of reading the serial data signal in a serial clock cycle under the control of the system clock signal. The processor can complete the operation of reading the serial data signal without executing any interrupting process.
Compared with the conventional method, which needs to call the interrupt service function to make the processor perform the interrupting process, the method of this embodiment can omit the conventional pushing, jumping and popping operations for the program address. Therefore, the time of waiting for processing the received data can be effectively shortened so that the speed for receiving data is increased.
In addition, both of the rising edges and the falling edges of the serial clock signal can trigger the interrupt service function in the conventional method, so the conventional method has to finish the operation of reading one bit of data between a rising edge and a neighboring falling edge of the serial clock signal. Since this embodiment needs not to perform the interrupt service function, it is unnecessary to complete the operation of reading one bit of data between a rising edge and a falling edge at one timing pulse of the serial clock signal (typically equal to one half of the serial clock cycle), like the prior art. Therefore, this embodiment only has to finish the operation of reading one bit of data in one serial clock cycle. Consequently, this embodiment has sufficient time for reading one bit of data. More particularly, the main program may further execute operations associated with a read bit in the remaining time after reading one bit during one serial clock cycle of the serial clock signal, thereby correspondingly increasing the efficiency of the receiving terminal.
Thereafter, in step 530, the bit is stored in the register.
Then, in step 630, values corresponding to the m bits are sequentially generated, and an addition result is obtained by performing an arithmetic addition operation (ADD) or a logic addition operation (AND) for the m values, and then stored to a register. In step 640, it is determined whether the m bits have been completely stored or not. If not, the procedure goes back to the step 620 to continue reading the remaining bits. If yes, a first acknowledging bit is outputted to a transmitting terminal in step 650.
In the method for decrypting the serial transmission signal according to the embodiments of the invention, the receiving terminal, in advance, sets the field of the bits of the serial data signal to be received. Therefore, the receiving terminal can read one bit of data in one serial clock cycle of the serial clock signal without using any interrupt service function, pushing command or jumping command and without waiting. In addition, it is unnecessary to finish a reading operation for one bit between a rising edge and a falling edge at one timing pulse of the serial clock signal, so the receiving terminal can further execute associated operations during the remaining time in one serial clock cycle, thereby correspondingly increasing the efficiency of the receiving terminal.
In addition, the method for decrypting the serial transmission signal according to the invention further directly stores each received bit to one corresponding position in the register by the addition operation. Thus, multiple rotation commands can be omitted, the calculation loading and the power consumption of the receiving terminal can be reduced, and the serial transmission signal can be rapidly decrypted; in addition, the cost and the power loss of the receiving terminal can be decreased.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 96134749 A | Sep 2007 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 3757261 | Sather | Sep 1973 | A |
| 4023019 | Leibowitz et al. | May 1977 | A |
| 4246642 | Magill | Jan 1981 | A |
| 4336600 | Houdard et al. | Jun 1982 | A |
| 4644502 | Kawashima | Feb 1987 | A |
| 4747139 | Taaffe | May 1988 | A |
| 4841466 | Christopher | Jun 1989 | A |
| 5313469 | Adham et al. | May 1994 | A |
| 5440702 | Brewer et al. | Aug 1995 | A |
| 5507001 | Nishizawa | Apr 1996 | A |
| 5621901 | Morriss et al. | Apr 1997 | A |
| 5623610 | Knoll et al. | Apr 1997 | A |
| 5694555 | Morriss et al. | Dec 1997 | A |
| 5742847 | Knoll et al. | Apr 1998 | A |
| 5903737 | Han | May 1999 | A |
| 6282558 | Kabuo | Aug 2001 | B1 |
| 6861981 | Park et al. | Mar 2005 | B2 |
| 6915335 | Chen et al. | Jul 2005 | B1 |
| 7373523 | Moritz | May 2008 | B1 |
| 7441060 | Gower et al. | Oct 2008 | B2 |
| 7526655 | Gammel et al. | Apr 2009 | B2 |
| 7610423 | Gower et al. | Oct 2009 | B2 |
| 7673338 | Osburn et al. | Mar 2010 | B1 |
| 7697692 | Takata et al. | Apr 2010 | B2 |
| 7826402 | Lin | Nov 2010 | B2 |
| 20020133631 | Yun | Sep 2002 | A1 |
| 20040120516 | Chen et al. | Jun 2004 | A1 |
| 20050050348 | Chin | Mar 2005 | A1 |
| 20070032193 | Wada et al. | Feb 2007 | A1 |
| 20070127431 | Eun et al. | Jun 2007 | A1 |
| 20070294509 | Sauer | Dec 2007 | A1 |
| 20080049934 | Onoda et al. | Feb 2008 | A1 |
| 20080288808 | Moyer | Nov 2008 | A1 |
| Number | Date | Country |
|---|---|---|
| 0304841 | Mar 1989 | EP |
| Number | Date | Country | |
|---|---|---|---|
| 20090074186 A1 | Mar 2009 | US |
