Claims
- 1. A method of satisfying circuit timing requirements during a circuit design process, comprising the steps of:
receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.
- 2. The method of claim 1 further including:
reporting said validity to said circuit design process.
- 3. The method of claim 1 wherein said circuit design process is a scheduler/binder.
- 4. The method of claim 1 wherein the hardware structural representation is fine-grained.
- 5. The method of claim 1 wherein the hardware structural representation is coarse-grained.
- 6. The method of claim 1 wherein the hardware structural representation is persistent and is incrementally updated every time a new alternative is received.
- 7. The method of claim 1 wherein the hardware structural representation is built from scratch every time said validity determination is performed.
- 8. The method of claim 1 wherein said validity determination is performed using timing analysis.
- 9. The method of claim 1 wherein the timing analysis is performed on the entire hardware structural representation.
- 10. The method of claim 6 wherein the timing analysis is performed on that portion of the hardware structural representation whose timing is changed as a result of the update to the hardware structural representation.
- 11. The method of claim 1 wherein the parameters for said delay characteristic functions are estimated using the hardware structural representation.
- 12. The method of claim 11 wherein the parameters include fan-in at each hardware resource.
- 13. The method of claim 11 wherein the parameters include fan-out capacitance for each hardware resource.
- 14. The method of claim 11 wherein the parameters include width of each hardware resource.
- 15. The method of claim 1 wherein the delay characteristics include Δini, Δouti, and Δthrui,j.
- 16. The method of claim 1 wherein said clock cycle-time constraint is a clock period.
- 17. The method of claim 1 wherein the said clock cycle-time constraint is a clock frequency.
- 18. A method of satisfying circuit timing requirements during a circuit design process, comprising:
receiving a clock cycle-time constraint; receiving area-delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining a comparative cost of the design, while ensuring that the clock cycle-time constraints are still met, by trading-off area with delay of the hardware resources present in the hardware structural representation of the program graph.
- 19. The method of claim 18 wherein the area-delay characteristics include area-delay trade-off curves.
- 20. The method of claim 19 wherein the area-delay trade-off curves are expressed as tuples.
- 21. The method of claim 19 wherein the area-delay trade-off curves are expressed as a closed-form formula.
- 22. The method of claim 18 wherein the said trading-off is done using numerical optimization.
- 23. The method of claim 18 wherein the said trading-off is done using time-budgeting.
- 24. A computer program stored on a computer readable media, the computer program for satisfying circuit timing requirements during a circuit design process, the computer program comprising:
computer code for receiving a clock cycle-time constraint; computer code for receiving delay characteristics of hardware resources from a macrocell library; computer code for receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and computer code for determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is related to commonly assigned U.S. patent application Ser. No. ______ [Attorney Docket No. 100200559-1] entitled “SYSTEM FOR AND METHOD OF CLOCK CYCLE-TIME ANALYSIS USING MODE-SLICING MECHANISM,” and U.S. patent application Ser. No. ______ [Attorney Docket No. 100200560-1] entitled “METHOD OF USING CLOCK CYCLE-TIME IN DETERMINING LOOP SCHEDULES DURING CIRCUIT DESIGN,” filed concurrently herewith, the disclosures of which are hereby incorporated by reference in their entireties.