Patent Application
20160004592
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2014-136032, filed on Jul. 1, 2014, the entire contents of which are incorporated herein by reference.
The embodiment discussed herein is related to a method for detecting an error of data, a storage device, and a recording medium.
As an adapter card serving as an interface (IF) with a host device, a storage device provided with a channel adapter (CA) is known. As related art, Japanese Laid-open Patent Publication No. 2010-191594, Japanese Laid-open Patent Publication No. 2012-88758, and Japanese Laid-open Patent Publication No. 2011-176894 are disclosed, for example.
According to an aspect of the invention, a method for detecting an error of data by a storage device including a storage configured to provide a storage region for a process by a host device and a buffer memory configured to temporarily store data that is transferred between the host device and the storage, the method includes storing, by a processor that is configured to avoid adding the error correcting code to the data when the data passes through the inside of the processor, the data received from the host device and an error correcting code in the buffer memory; reading the data from the buffer memory and transmitting the read data to a calculating circuit; calculating, by the calculating circuit, a first checksum of the data and transmitting the data to the processor; storing, by the processor, the data and the error correcting code in a sub memory; reading the data from the sub memory and transmitting the read data to the calculating circuit through the processor; calculating, by the calculating circuit, a second checksum of the data received from the sub memory and having passed through the processor; and determining, by the processor, whether an error of the data occurs within the processor by comparing the first checksum with the second checksum.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
In a conventional CA, a part at which data is not protected by parity or the like exists. Thus, when data passes through the interested part, the data may be garbled on a bus. Since the fact that the data is garbled in the CA is not detected as an error, the erroneous data may be written in a memory device. If a part at which data is not protected by parity or the like exists, it is desirable that the identity of the data to be written in the memory device be guaranteed.
Hereinafter, an embodiment of a communication control device, a storage device, and a communication control program is described with reference to the accompanying drawings. The embodiment is merely exemplified and does not intend to exclude the application of various modified examples and techniques that are not clearly described in the embodiment. Specifically, the embodiment may be variously modified and changed without departing from the gist of the embodiment.
The drawings do not indicate only constituent elements illustrated in the drawings and may indicate that other functions and the like are included.
In the drawings, the same parts are represented by the same reference numerals and symbols, and a repetitive description thereof is omitted.
A storage system 100 provides a storage region to a host device (higher-level device) 3. The storage system 100 includes the host device 3 and a storage device 10.
The host device 3 is a computer having a server function. The host device 3 accesses the storage device 10 in order to read and write data from and in the storage device 10 in a variable length (CKD) format.
The storage device 10 has a memory device 2 (described later) and provides a storage region to the host device 3. The storage device 10 includes a CA (communication control device or communication controller) 1, the memory device 2, and a controller module (CM) 4.
The memory device 2 is a known device for storing data, while data is able to be read from and written in the memory device 2. The memory device 2 is, for example, a hard disk drive (HDD) or a solid state drive (SSD). Although the single memory device 2 is illustrated in the example of
The CM 4 is a device configured to execute control of various types. The CM 4 executes the control of the various types in accordance with a request (access control signal, hereinafter referred to as host I/O) to access the memory device 2 from the host device 3. Specifically, the CM 4 writes and reads data in and from the memory device 2 based on block access from the CA 1.
The CA 1 is an interface controller that connects the host device 3 and the memory device 2 to each other so as to enable the host device 3 and the memory device 2 to communicate with each other. The CA 1 receives data transmitted by the host device 3 or the memory device 2 and temporarily stores the data in a data buffer 140. After that, the CA 1 transfers the data to the CM 4 and transfers data received from the CM 4 to the host device 3. Specifically, the CA 1 controls input and output (I/O) of data from and to the external devices including the host device 3. The CA 1 has a function of converting variable-length access between the CA 1 and the host device 3 and block access between the CA 1 and the CM 4 into each other. In the example illustrated in
A storage system 100a illustrated in
The host device 3a is a computer having a server function, for example.
The memory device 2a is a known device for storing data, while data is able to be read from and written in the memory device 2a. The memory device 2a is, for example, an HDD or an SSD.
The CA is is an interface controller that connects the host device 3a and the memory device 2a to each other so as to enable the host device 3a and the memory device 2a to communicate with each other. The CA is receives data transmitted by the host device 3a and the memory device 2a and temporarily stores the data in a data buffer 140a. After that, the CA is transfers the data to a CM (not illustrated) included in the storage device and transfers data received from the CM to the host device 3a. Specifically, the CA is controls input and output (I/O) of data from and to the external devices including the host device 3a.
The CA is includes a micro-processing unit (MPU) 110a, a chip select (CS) memory 120a, a field-programmable gate array (FPGA) 130a, the data buffer 140a, a switch (SW) 150a, and an IF chip 160a.
The IF chip 160a controls a fiber channel (FC) protocol and provides two FC interfaces for the single IF chip 160a.
The SW 150a switches between a data path located between the IF chip 160a and the MPU 110a and a data path located between the MPU 110a and the FPGA 130a.
The data buffer 140a is a memory device configured to temporarily stores data that is transmitted and received between the host device 3a and the CM (not illustrated).
The FPGA 130a is an integrated circuit having a configuration that is arbitrarily settable. The FPGA 130a transmits and receives data to and from the CM (not illustrated). The FPGA 130a generates a check code and executes checking. Access between the host device 3a and the CA is is count key data (CKD) access (variable-length access), while access between the CA is and the memory device 2a is block access. The CA is has a function of converting the variable-length access and the block access into each other.
The CS memory 120a is a memory device that provides a storage region to the MPU 110a.
The MPU 110a is a processing device configured to execute control of various types and calculation of various types. The MPU 110a executes an operating system (OS) or program stored in the CS memory 120a and thereby achieves various functions.
The flow of data in the storage system according to the technique related to the embodiment is described with reference to
When the host device 3a issues write I/O to the memory device 2a, data related to the write I/O is temporarily stored in the data buffer 140a (refer to reference symbol C1 illustrated in
The data stored in the data buffer 140a includes a plurality of valid data items to be written in the memory device 2a and a plurality of invalid data items to be discarded by the MPU 110a as described later (refer to reference symbol C2 illustrated in
The MPU 110a reads the data written in the data buffer 140a and writes the read data in the CS memory 120a. In this case, the MPU 110a extracts only the valid data items from the read data, discards the invalid data items, and writes the valid data items in the CS memory 120a (refer to reference symbol C3 illustrated in
The data written in the CS memory 120a includes only the valid data items (refer to reference symbol C4 illustrated in
The MPU 110a reads the data written in the CS memory 120a and causes the read data to be temporarily stored in the data buffer 140a (refer to reference symbols C5 and C6 illustrated in
Then, the data stored in the data buffer 140a is written in the memory device 2a through the CM (not illustrated) (refer to reference symbols C7 and C8 illustrated in
Since ECRC is not added to the data transmitted on the bus within the MPU 110a included in the CA is according to the technique related to the embodiment, the data is not protected by parity or the like and may be garbled on the bus. Since the fact that the data is garbled within the MPU 110a is not detected as an error, the erroneous data may be written in the memory device 2a. Especially, if a chain data function is used to divide data into eight or more data items, write I/O is issued, and the data is garbled on the bus within the MPU 110a, the erroneous data may be written in the memory device 2a.
On the other hand, in an example of the embodiment, as illustrated in
The SFP modules 162 are interface modules that connect the CA 1 (storage device 10) to the host device 3 through optical fibers so as to enable the CA 1 (storage device 10) and the host device 3 to communicate with each other. The communication lines between the CA 1 (storage device 10) and the host device 3 are not limited to the optical fibers. The CA 1 may include various interface modules other than the SFP modules 162.
The FC controller 161 controls a FC protocol and provides two FC interfaces for the single FC controller 161, for example. The communication protocol between the CA 1 (storage device 10) and the host device 3 is not limited to the FC protocol. The CA 1 may include controllers that are not the FC controller 161 and support various communication protocols.
For example, the FC controller 161 and the SFP modules 162 function as the IF chip 160, as illustrated in
The SW 150 switches between a data path located between the FC controller 161 and the MPU 110 and a data path located between the MPU 110 and the FPGA 130. In the example of the embodiment, the SW 150 connects the FC controller 161, the MPU 110, and the FPGA 130 to each other through a PCI Express link so as to enable the FC controller 161, the MPU 110, and the FPGA 130 to communicate with each other, for example.
The SDRAMs 141 are semiconductor memories. For example, the SDRAMs 141 are double-data-rate SDRAMs (DDR SDRAMs). The SDRAMs 141 temporarily store data transmitted and to be received between the host device 3 and the CM 4. The five SDRAMs 141 illustrated in
The FPGA 130 is an integrated circuit having a configuration that is arbitrarily settable. The FPGA 130 transmits and receives data to and from the CM 4. The FPGA 130 generates a check code and executes checking. Access between the host device 3 and the CA 1 is count key data (CKD) access (variable-length access), while access between the CA 1, the CM 4, and the memory device 2 is block access. The FPGA 130 has a function of converting the variable-length access and the block access into each other.
As illustrated in
The first calculator 131 calculates a checksum of data transmitted from the host device 3. Specifically, when the MPU 110 reads data transmitted by the host device 3 and stored in the data buffer 140, the first calculator 131 calculates, as a transmission checksum, a checksum of the data read by the MPU 110. For example, when receiving, from the MPU 110, a request to read data stored at addresses 0x0000 to 0x0FFF of the data buffer 140, the first calculator 131 calculates the transmission checksum. The first calculator 131 causes the calculated transmission checksum to be stored in the first storage unit 132. Since the checksum may be calculated using any of known various methods, a description of the calculation method is omitted.
The first storage unit 132 is a storage region for storing a transmission checksum calculated by the first calculator 131. The first storage unit 132 is a register included in the FPGA 130.
The second calculator 133 calculates a checksum of data to be transmitted to the memory device 2. Specifically, when the MPU 110 writes data in the data buffer 140, the second calculator 133 calculates, as a reception checksum, a checksum of the data written by the MPU 110. For example, when receiving, from the MPU 110, a request to write data at the addresses 0x0000 to 0x0FFF of the data buffer 140 and addresses 0x8000 to 0x8FFF of the data buffer 140, the second calculator 133 calculates the reception checksum. The second calculator 133 causes the calculated reception checksum to be stored in the second storage unit 134.
The second storage unit 134 is a storage region for storing a reception checksum calculated by the second calculator 133. The second storage unit 134 is a register included in the FPGA 130.
The address converter 135 associates (converts) physical addresses of the data buffer 140 with (into) virtual addresses. Thus, the MPU 110 may specify the virtual addresses and read and write data from and in the data buffer 140. Details of the function of the address converter 135 are described later in a first modified example (described later) of the embodiment.
In the example of the embodiment, the FPGA 130 may not have the function as the address converter 135. In this case, the MPU 110 specifies physical addresses of the data buffer 140 and reads and writes data from and in the data buffer 140.
The SDRAMs 121 are semiconductor memories. For example, the SDRAMs 121 are DDR SDRAMs. The SDRAMs 121 provide storage regions to the MPU 110. The three SDRAMs 121 illustrated in
The CS memory 120 stores data read by the MPU 110 from the data buffer 140. In the example of
The MPU 110 is a processing device configured to execute control of various types of control and calculation of various types. The MPU 110 executes an OS or program stored in the CS memory 120 and thereby achieves various functions such as communication with the CM 4 and control of the CA 1. Specifically, the MPU 110 functions as a reading and writing unit 111, a comparator 112, an error output unit 113, and an inhibitor 114, as illustrated in
A program (communication control program) that achieves functions as the reading and writing unit 111, the comparator 112, the error output unit 113, and the inhibitor 114 is provided while being stored in a computer-readable recording medium such as a flexible disk, a CD (CD-ROM, CD-R, CD-RW, or the like), a DVD (DVD-ROM, DVD-RAM, DVD-R, DVD+R, DVD-RW, DVD+RW, HD DVD, or the like), a Blu-ray disc, a magnetic disk, an optical disc, or a magnetic optical disc. A computer reads the program through a reading device (not illustrated) from the recording medium, transfers the program to an internal or external recording device, causes the program to be stored in the internal or external recording device, and uses the program. The program may be stored in a memory device (recording medium) such as a magnetic disk, an optical disc, or a magnetic optical disc and provided to the computer from the memory device through a communication path.
In order to achieve the functions as the reading and writing unit 111, the comparator 112, the error output unit 113, and the inhibitor 114, the program stored in the internal memory device (CS memory 120 in the embodiment) is executed by a microprocessor (MPU 110 in the embodiment) of the computer. In this case, the program stored in the recording medium may be read and executed by the computer.
The reading and writing unit 111 reads and writes data from and in the CS memory 120, the first storage unit 132, the second storage unit 134, and the data buffer 140.
Specifically, the reading and writing unit 111 reads data stored in the data buffer 140 and causes the read data to be stored in the CS memory 120.
The reading and writing unit 111 reads data written in the CS memory 120 and causes the read data to be stored in the data buffer 140.
The reading and writing unit 111 reads, from the first storage unit 132, a transmission checksum calculated by the first calculator 131 of the FPGA 130. Then, the reading and writing unit 111 reads, from the second storage unit 134, a reception checksum calculated by the second calculator 133 of the FPGA 130. When the reading and writing unit 111 reads data stored in the data buffer 140, the reading and writing unit 111 clears values stored in the first and second storage units 132 and 134 of the FPGA 130 to “0”.
The comparator 112 compares the transmission checksum read by the reading and writing unit 111 with the reception checksum read by the reading and writing unit 111. Specifically, the comparator 112 determines whether or not the transmission checksum stored in the first storage unit 132 matches the reception checksum stored in the second storage unit 134.
If the transmission checksum does not match the reception checksum as a result of the comparison made by the comparator 112, the error output unit 113 outputs an error. For example, if the comparator 112 determines that the transmission checksum does not match the reception checksum, the error output unit 113 outputs the error to a display device (not illustrated). Thus, the error output unit 113 notifies a user that an error such as garbling of data to be written in the memory device 2 by I/O provided by the host device 3 occurs.
If the transmission checksum does not match the reception checksum as a result of the comparison made by the comparator 112, the inhibitor 114 inhibits the data from being transmitted to the memory device 2. For example, if the comparator 112 determines that the transmission checksum does not match the reception checksum, the inhibitor 114 issues an inhibition signal to the CM 4 and thereby inhibits the data stored in the data buffer 140 from being written in the memory device 2. Thus, the inhibitor 114 inhibits data that may be garbled in the MPU 110 from being written in the memory device 2.
A data guarantee control process by the storage device according to the embodiment is described with reference to
In the example illustrated in
When I/O is issued by the host device 3 and data is stored in the data buffer 140, the reading and writing unit 111 of the MPU 110 clears (initializes) values stored in the transmission checksum register 132 and reception checksum register 134 to “0” (refer to reference symbol A1 illustrated in
The reading and writing unit 111 reads the data stored in the data buffer 140 (refer to reference symbol A2 illustrated in
The reading and writing unit 111 of the MPU 110 writes the data read from the data buffer 140 in the CS memory 120 (refer to reference symbol A3 illustrated in
The first calculator 131 of the FPGA 130 calculates a checksum of the data read by the MPU 110 from the data buffer 140. Then, the first calculator 131 causes the calculated checksum to be stored as a transmission checksum in the transmission checksum register 132 (refer to reference symbol A4 illustrated in
The reading and writing unit 111 of the MPU 110 reads the data written in the CS memory 120 (refer to reference symbol A5 illustrated in
The reading and writing unit 111 of the MPU 110 writes the data read from the CS memory 120 in the data buffer 140 (refer to reference symbol A6 illustrated in
The second calculator 133 of the FPGA 130 calculates a checksum of the data written by the MPU 110 in the data buffer 140. Then, the second calculator 133 causes the calculated checksum to be stored as a reception checksum in the reception checksum register 134 (refer to reference symbol A7 illustrated in
The reading and writing unit 111 of the MPU 110 reads the transmission checksum stored in the transmission checksum register 132 and the reception checksum stored in the reception checksum register 134. Specifically, the reading and writing unit 111 issues a request to read the transmission checksum and the reception checksum to the FPGA 130 (refer to S13 illustrated in
The comparator 112 of the MPU 110 compares the transmission checksum read by the reading and writing unit 111 with the reception checksum read by the reading and writing unit 111 (refer to reference symbol A8 illustrated in
If the transmission checksum matches the reception checksum as a result of the comparison made by the comparator 112, the data stored in the data buffer 140 is transmitted to the memory device 2.
On the other hand, if the transmission checksum does not match the reception checksum as a result of the comparison made by the comparator 112, the error output unit 113 of the MPU 110 outputs an error. If the transmission checksum does not match the reception checksum as a result of the comparison made by the comparator 112, the inhibitor 114 of the MPU 110 may inhibit the data from being transmitted to the memory device 2.
The communication control device 1 (storage device 10) according to the aforementioned example of the embodiment may provide the following effects, for example.
The first calculator 131 calculates a first value related to data read by the reading and writing unit 111 from the data storage unit 140. The second calculator 133 calculates a second value related to data written by the reading and writing unit 111 in the data storage unit 140. Then, the comparator 112 compares the first value stored in the first storage unit 132 with the second value stored in the second storage unit 134. The identity of the data to be written in the memory device 2 may be guaranteed by the comparison made by the comparator 112.
The error output unit 113 outputs an error if the first value does not match the second value as a result of the comparison made by the comparator 112. Thus, the user may know that an error such as garbling of data to be written in the memory device 2 occurs.
If the first value does not match the second value as a result of the comparison made by the comparator 112, the inhibitor 114 inhibits the data from being transmitted to the memory device 2. It is, therefore, possible to inhibit data within the memory device 2 from being damaged by the writing of erroneous data such as garbled data in the memory device 2.
Since a function of protecting data on the internal bus of the MPU 110 is not provided, it is possible to inhibit a manufacturing cost from increasing due to an increase in the size of a circuit.
In addition, since the protection of data on the internal bus of the MPU 110 is not provided, it is possible to inhibit performance such as a rate of transferring data from being reduced.
In the example of
In the first modified example of the embodiment, the data guarantee control process is made redundant and executed.
The address converter 135 of the FPGA 130 associates (converts) physical addresses of the data buffer 140 with (into) redundant virtual addresses. In the example illustrated in
Specifically, the address converter 135 defines three storage regions within the data buffer 140. The address converter 135 sets data buffer virtual address spaces 142 corresponding to the three storage regions.
The FPGA 130 includes the multiple pairs of transmission checksum registers 132 and reception checksum registers 134, while the pairs correspond to the virtual address spaces made redundant by the address converter 135. In the example illustrated in
Hereinafter, when one of the transmission checksum registers is to be identified, the transmission checksum register is represented as the “transmission checksum register #1”, the “transmission checksum register #2”, or the “transmission checksum register #3”. However, when any of the transmission checksum registers is to be identified, the transmission checksum register is represented as a “transmission checksum register 132”. Hereinafter, when one of the reception checksum registers is to be identified, the reception checksum register is represented as the “reception checksum register #1”, the “reception checksum register #2”, or the “reception checksum register #3”. However, when any of the reception checksum registers is to be identified, the reception checksum register is represented as a “reception checksum register 134”.
The reading and writing unit 111 of the MPU 110 sets a memory map (not illustrated) stored in, for example, the SDRAM 121 so as to ensure that the set memory map is able to be referenced. Then, the reading and writing unit 111 references the stored memory map and thereby recognizes the data buffer virtual address spaces 142 obtained by making a physical address space of the data buffer 140 redundant. In the example illustrated in
Hereinafter, when one of the data buffer virtual address spaces is to be identified, the data buffer virtual address space is represented as the “data buffer virtual address space #1”, the “data buffer virtual address space #2”, or the “data buffer virtual address space #3”. However, when any of the data buffer virtual address spaces is to be identified, the data buffer virtual address space is represented as a “data buffer virtual address space 142”.
A data capacity (of 256 MB in the example illustrated in
In the example illustrated in
In the first modified example of the embodiment, data to be read and written by the reading and writing unit 111 of the MPU 110 from and in the data buffer virtual address spaces #1 to #3 specified by the reading and writing unit 111 is represented as data #1 to #3 in some cases. In the first modified example of the embodiment, transmission checksums stored in the transmission checksum registers #1 to #3 are represented as transmission checksums #1 to #3 in some cases, and reception checksums stored in the reception checksum registers #1 to #3 are represented as reception checksums #1 to #3 in some cases.
The first calculator 131 and second calculator 133 of the FPGA 130 cause a transmission checksum and reception checksum calculated for the same data to be stored in a single pair of a transmission checksum register 132 and a reception checksum register 134.
Specifically, when the MPU 110 reads the data #1 from the data buffer virtual address space #1 specified by the MPU 110, the first calculator 131 calculates the transmission checksum #1 and causes the calculated transmission checksum #1 to be stored in the transmission checksum register #1. When the MPU 110 writes the data #1 in the data buffer virtual address space #1 specified by the MPU 110, the second calculator 133 calculates the reception checksum #1 and causes the calculated reception checksum #1 to be stored in the reception checksum register #1.
When the MPU 110 reads the data #2 from the data buffer virtual address space #2 specified by the MPU 110, the first calculator 131 calculates the transmission checksum #2 and causes the calculated transmission checksum #2 to be stored in the transmission checksum register #2. When the MPU 110 writes the data #2 in the data buffer virtual address space #2 specified by the MPU 110, the second calculator 133 calculates the reception checksum #2 and causes the calculated reception checksum #2 to be stored in the reception checksum register #2.
When the MPU 110 reads the data #3 from the data buffer virtual address space #3 specified by the MPU 110, the first calculator 131 calculates the transmission checksum #3 and causes the calculated transmission checksum #3 to be stored in the transmission checksum register #3. When the MPU 110 writes the data #3 in the data buffer virtual address space #3 specified by the MPU 110, the second calculator 133 calculates the reception checksum #3 and causes the calculated reception checksum #3 to be stored in the reception checksum register #3.
The comparator 112 of the MPU 110 compares a transmission checksum with a reception checksum for each of the pairs of transmission checksum registers 132 and reception checksum registers 134.
Specifically, the comparator 112 compares the transmission checksum #1 stored in the transmission checksum register #1 with the reception checksum #1 stored in the reception checksum register #1. The comparator 112 compares the transmission checksum #2 stored in the transmission checksum register #2 with the reception checksum #2 stored in the reception checksum register #2. The comparator 112 compares the transmission checksum #3 stored in the transmission checksum register #3 with the reception checksum #3 stored in the reception checksum register #3.
An example of the data guarantee control process by the storage device according to the first modified example of the embodiment is described with reference to sequence diagrams (S21 to S35 and S41 to S55) of
In the example illustrated in
When I/O is issued by the host device 3 and the data #1 is stored in the data buffer 140, the reading and writing unit 111 of the MPU 110 clears (initializes) values stored in the transmission checksum register #1 and reception checksum register #1 to “0” (refer to S21 illustrated in
The reading and writing unit 111 reads the data #1 stored in the data buffer 140. Specifically, the reading and writing unit 111 specifies the data buffer virtual address space #1 and issues, to the FPGA 130, a request to read the data #1 stored (at, for example, the addresses 0x0000 to 0x0100) in the data buffer 140 (refer to S22 illustrated in
The reading and writing unit 111 of the MPU 110 issues a request to write the data #1 to the CS memory 120 and writes the read data #1 in the CS memory 120 (refer to S26 illustrated in
The first calculator 131 of the FPGA 130 calculates a checksum of the data #1 read by the MPU 110 from the data buffer 140 and causes the calculated checksum to be stored as the transmission checksum #1 in the transmission checksum register #1 (refer to S27 illustrated in
When I/O is issued by the host device 3 and the data #2 is stored in the data buffer 140, the reading and writing unit 111 of the MPU 110 clears (initializes) values stored in the transmission checksum register #2 and reception checksum register #2 to “0” (refer to S41 illustrated in
The reading and writing unit 111 reads the data #1 written in the CS memory 120. Specifically, the reading and writing unit 111 issues a request to read the data #1 to the CS memory 120 (refer to S28 illustrated in
The reading and writing unit 111 reads the data #2 stored in the data buffer 140. Specifically, the reading and writing unit 111 specifies the data buffer virtual address space #2 and issues a request to read the data #2 stored (at, for example, addresses 0x1100 to 0x1200) in the data buffer 140 to the FPGA 130 (refer to S42 illustrated in
The reading and writing unit 111 of the MPU 110 issues a request to write the data #2 to the CS memory 120 and writes the read data #2 in the CS memory 120 (refer to S46 illustrated in
The first calculator 131 of the FPGA 130 calculates a checksum of the data #2 read by the MPU 110 from the data buffer 140. Then, the first calculator 131 causes the calculated checksum to be stored as the transmission checksum #2 in the transmission checksum register #2 (refer to S47 illustrated in
The reading and writing unit 111 of the MPU 110 writes the data #1 read from the CS memory 120 in the data buffer 140. Specifically, the reading and writing unit 111 specifies the data buffer virtual address space #1 and issues, to the FPGA 130, a request to write the data #1 (at, for example, the addresses 0x0000 to 0x0100) in the data buffer 140 (refer to S30 illustrated in
The second calculator 133 of the FPGA 130 calculates a checksum of the data #1 written by the MPU 110 in the data buffer 140. Then, the second calculator 133 causes the calculated checksum to be stored as the reception checksum #1 in the reception checksum register #1 (refer to S32 illustrated in
The reading and writing unit 111 of the MPU 110 reads the data #2 written in the CS memory 120. Specifically, the reading and writing unit 111 issues a request to read the data #2 to the CS memory 120 (refer to S48 illustrated in
The reading and writing unit 111 of the MPU 110 reads the transmission checksum #1 stored in the transmission checksum register #1 and the reception checksum #1 stored in the reception checksum register #1. Specifically, the reading and writing unit 111 issues a request to read the transmission checksum #1 and the reception checksum #1 to the FPGA 130 (refer to S33 illustrated in
The comparator 112 of the MPU 110 compares the transmission checksum #1 read by the reading and writing unit 111 with the reception checksum #1 read by the reading and writing unit 111 (refer to S35 illustrated in
If the transmission checksum #1 matches the reception checksum #1 as a result of the comparison made by the comparator 112, the data #1 stored in the data buffer 140 is transmitted to the memory device 2.
On the other hand, if the transmission checksum #1 does not match the reception checksum #1 as a result of the comparison made by the comparator 112, the error output unit 113 of the MPU 110 outputs an error. If the transmission checksum #1 does not match the reception checksum #1 as a result of the comparison made by the comparator 112, the inhibitor 114 of the MPU 110 may inhibit the data #1 from being transmitted to the memory device 2.
The reading and writing unit 111 of the MPU 110 writes the data #2 read from the CS memory 120 in the data buffer 140. Specifically, the reading and writing unit 111 specifies the data buffer virtual address space #2 and issues a request to write the data #2 (at, for example, the addresses 0x1100 to 0x1200) in the data buffer 140 to the FPGA 130 (refer to S50 illustrated in
The second calculator 133 of the FPGA 130 calculates a checksum of the data #2 written by the MPU 110 in the data buffer 140. Then, the second calculator 133 causes the calculated checksum to be stored as the reception checksum #2 in the reception checksum register #2 (refer to S52 illustrated in
The reading and writing unit 111 of the MPU 110 reads the transmission checksum #2 stored in the transmission checksum register #2 and the reception checksum #2 stored in the reception checksum register #2. Specifically, the reading and writing unit 111 issues a request to read the transmission checksum #2 and the reception checksum #2 to the FPGA 130 (refer to S53 illustrated in
The comparator 112 of the MPU 110 compares the transmission checksum #2 read by the reading and writing unit 111 with the reception checksum #2 read by the reading and writing unit 111 (refer to S55 illustrated in
If the transmission checksum #2 matches the reception checksum #2 as a result of the comparison made by the comparator 112, the data #2 stored in the data buffer 140 is transmitted to the memory device 2.
On the other hand, if the transmission checksum #2 does not match the reception checksum #2 as a result of the comparison made by the comparator 112, the error output unit 113 of the MPU 110 outputs an error. If the transmission checksum #2 does not match the reception checksum #2 as a result of the comparison made by the comparator 112, the inhibitor 114 of the MPU 110 may inhibit the data #2 from being transmitted to the memory device 2.
The communication control device 1 (storage device 10) according to the first modified example of the embodiment may provide the effects described above in the example of the embodiment and the following effects, for example.
The address converter 135 associates physical addresses of the data storage unit 140 with redundant virtual addresses. Then, the reading and writing unit 111 specifies virtual addresses and reads and writes data from and in the data storage unit 140. Thus, when I/O is made redundant and issued by the higher-level device 3, processes of transferring a plurality of data items may be made redundant and executed in parallel.
The comparator 112 makes a comparison for each of the pairs of first and second storage units 132 and 134 corresponding to redundant virtual address spaces. Thus, when I/O is made redundant and issued by the higher-level device 3, the data guarantee control process may be made redundant and executed on a plurality of data items in parallel.
As described with reference to
In the aforementioned example of the embodiment, if data transmitted by the host device 3 includes invalid data, a value of a transmission checksum calculated by the first calculator 131 of the FPGA 130 before the discarding of the invalid data is different from a value of a reception checksum calculated by the second calculator 133 of the FPGA 130 after the discarding of the invalid data. Thus, regardless of the fact that an error such as garbling of the data on the bus within the MPU 110 does not occur, the comparator 112 of the MPU 110 detects that the transmission checksum does not match the reception checksum.
In the second modified example of the embodiment, even if data transmitted by the host device 3 includes invalid data, the reading and writing unit 111 of the MPU 110 writes the invalid data as dummy data in the FPGA 130. For example, a data buffer virtual address space for dummy writing is defined, as well as the data buffer virtual address spaces #1 to #3 illustrated in
The data buffer virtual address space for dummy writing is specified and the dummy data written in the data buffer virtual address space for dummy writing is set so as not to be written in the data buffer 140. For example, when receiving a request to write data at the addresses 0x0000 to 0x0FFF of the data buffer 140 from the MPU 110, the address converter 135 of the FPGA 130 writes the data corresponding to the write request in the data buffer 140. When receiving a request to write data at the addresses 0x8000 to 0x8FFF of the data buffer 140 from the MPU 110, the address converter 135 does not write the data corresponding to the write request in the data buffer 140.
The second calculator 133 of the FPGA 130 calculates a reception checksum based on data (valid data) written by the MPU 110 in the data buffer 140 and the dummy data (invalid data) written by the MPU 110 in the FPGA 130.
Hereinafter, an example of the data guarantee control process by the storage device according to the second modified example of the embodiment is described with reference to
In the example of
In the example illustrated in
When I/O is issued by the host device 3 and the data #1 to #3 is stored in the data buffer 140, the reading and writing unit 111 of the MPU 110 clears (initializes) values stored in the transmission checksum registers 132 and reception checksum registers 134 to “0” (refer to S1 illustrated in
The reading and writing unit 111 issues a request to read the data #1 to #3 stored (at, for example, the addresses 0x0000 to 0x0100) in the data buffer 140 and reads the data #1 to #3 stored in the data buffer 140 (refer to reference symbol B1 illustrated in
The reading and writing unit 111 issues a write request to the CS memory 120 and writes the data #1 to #3 in the CS memory 120 (refer to S6 illustrated in
The first calculator 131 of the FPGA 130 calculates checksums of the data #1 to #3 read by the MPU 110 from the data buffer 140. Then, the first calculator 131 causes the calculated checksums to be stored as transmission checksums in the transmission checksum registers 132 (refer to reference symbol B2 illustrated in
The reading and writing unit 111 of the MPU 110 issues a read request to the CS memory 120 and extracts and reads the valid data #1 and #3 among the data #1 to #3 written in the CS memory 120 (refer to S8 and S9 illustrated in
The reading and writing unit 111 issues a request to write the data #1 and #3 (at, for example, the addresses 0x0000 to 0x0050) in the data buffer 140 and writes the data #1 and #3 read from the CS memory 120 in the data buffer 140 (refer to reference symbol B3 illustrated in
The second calculator 133 of the FPGA 130 calculates checksums of the data #1 and #3 written by the MPU 110 in the data buffer 140. Then, the second calculator 133 causes the calculated checksums to be stored as reception checksums in the reception checksum registers 134 (refer to reference symbol B4 illustrated in
The reading and writing unit 111 of the MPU 110 extracts and reads the invalid data #2 among the data #1 to #3 written in the CS memory 120. Specifically, the reading and writing unit 111 issues a request to read the data #2 to the CS memory 120 (refer to S61 illustrated in
The reading and writing unit 111 of the MPU 110 specifies the data buffer virtual address space (for example, virtual addresses corresponding to the physical addresses 0x8000 to 0x8050) for dummy writing to the FPGA 130 and issues a write request. Thus, the reading and writing unit 111 writes, as dummy data, the data #2 read from the CS memory 120 in the FPGA 130 (refer to reference symbol B5 illustrated in
The second calculator 133 of the FPGA 130 calculates reception checksums based on the data (valid data) #1 and #3 written by the MPU 110 in the data buffer 140 and the dummy data (invalid data) #2 written by the MPU 110 in the FPGA 130. Then, the second calculator 133 causes the calculated reception checksums to be stored in the reception checksum registers 134 (refer to reference symbol B6 illustrated in
An offset (for example, 0x8000) that represents dummy data is added to the data written by the MPU 110. Thus, the address converter 135 of the FPGA 130 discards the dummy data without transferring the dummy data to the data buffer 140.
The reading and writing unit 111 of the MPU 110 issues a request to read the transmission checksums and the reception checksums to the FPGA 130. Thus, the reading and writing unit 111 reads the transmission checksums stored in the transmission checksum registers 132 and the reception checksums stored in the reception checksum registers 134 (refer to reference symbol B7 illustrated in
The comparator 112 of the MPU 110 compares the transmission checksums read by the reading and writing unit 111 with the reception checksums read by the reading and writing unit 111 (refer to S15 illustrated in
If the transmission checksums match the reception checksums as a result of the comparison made by the comparator 112, the data #1 and #3 stored in the data buffer 140 is transmitted to the memory device 2.
On the other hand, if the transmission checksums do not match the reception checksums as a result of the comparison made by the comparator 112, the error output unit 113 of the MPU 110 outputs an error. If the transmission checksums do not match the reception checksums as a result of the comparison made by the comparator 112, the inhibitor 114 of the MPU 110 may inhibit the data #1 and #3 from being transmitted to the memory device 2.
The communication control device 1 (storage device 10) according to the second modified example of the embodiment may provide the effects described above in the example of the embodiment and the following effects, for example.
If data transmitted by the higher-level device 3 includes data that is not to be transmitted to the memory device 2, the second calculator 133 calculates a second value based on data written by the reading and writing unit 111 in the data storage unit 140 and the data that is not to be transmitted to the memory device 2. It is, therefore, possible to inhibit the comparator 112 from detecting that a transmission checksum does not match a reception checksum, regardless of the fact that an error such as garbling of data on the bus within the MPU 110 does not occur.
The reading and writing unit 111 specifies a specific address among virtual addresses and transmits, to the second calculator 133, the data that is not to be transmitted to the memory device 2. It is, therefore, possible to inhibit unwanted data from being transmitted to the memory device 2.
The technique disclosed herein is not limited to the aforementioned embodiment and may be variously modified without departing from the gist of the embodiment. At least one of the configurations according to the embodiment and at least one of the processes according to the embodiment may be selected or combined.
In the aforementioned example of the embodiment and the modified examples, the first calculator 131 and the second calculator 133 calculate checksums and the comparator 112 compares the checksums. The first calculator 131, the second calculator 133, and the comparator 112, however, are not limited to this. The first calculator 131 and the second calculator 133 may calculate various error detecting codes other than checksums, and the comparator 112 may compare the calculated error detecting codes.
In the aforementioned example of the embodiment and the modified examples, the MPU 110 have the functions as the comparator 112, the error output unit 113, and the inhibitor 114. The functions, however, are not limited to this. For example, the FPGA 130 may have the functions as the comparator 112, the error output unit 113, and the inhibitor 114.
In the aforementioned example of the embodiment and the modified examples, the reading and writing unit 111 specifies the data buffer virtual address space for dummy writing and writes dummy data in the FPGA 130. The reading and writing unit 111, however, is not limited to this. For example, the reading and writing unit 111 may specify the data buffer virtual address spaces 142 illustrated in
All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment of the present invention has been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-136032 | Jul 2014 | JP | national |
