This invention is directed towards creating a method for devices in a network to participate in an end-to-end measurement of latency and also determine segment by segment latency without additional messaging in the network.
When an Ethernet circuit (or other type of circuit) is activated in a network, there is a need to be able to obtain precise performance measurements to make sure the circuit is fully functional in accordance with the performance specification of the operator. Unidirectional (1-way) and bi-directional (2-way) delay measurements are an essential performance measurement that needs to be obtained as part of the service activation. These measurements are also very useful to measure the performance of the Ethernet circuit while IN SERVICE.
These measurements, though useful, do not take into account the multiple segments that may exist within a network path and give no information to isolate the segment delay within the absolute path. To find such a segment over a multi-segment path requires numerous tests, excessive messaging and time.
There is a need to be able to discover a segment by segment latency along a path when an end-to-end latency measurement is requested and not increase messaging as a by-product of this segment by segment measurement.
An example of a unidirectional (1-way) measurement is illustrated in
An example of a bi-directional (2-way) measurement is illustrated in
In accordance with one embodiment, a method of determining the latency of path segments in a communication network that uses multi-bit data packets comprises generating a test packet for use in determining the latency of path segments in the network; transmitting the test packet from a first device coupled to the network; storing in the test packet the time when a preselected bit in the test packet is transmitted from the first device; when the test packet is received by a second device coupled to the network, storing in the second device at least one of (a) the time when a preselected bit in the test packet is received by the second device and (b) the difference between (i) the time when the preselected bit in the test packet is transmitted from the first device and (ii) the time when the test packet is received by the second device. In one implementation, the time when a preselected bit in the test packet is received by the second device is stored in the second device, and the latency of the path segment between the first and second devices is determined to be the difference between the two stored times. In another implementation, the difference between (i) the time when the preselected bit in the test packet is transmitted from the first device and (ii) the time when the test packet is received by the second device, is stored in the second device, and the latency of the path segment between the first and second devices is determined by retrieving the difference from the second device.
The test packet may be transmitted serially from the second device to a plurality of additional devices coupled to the network. Each time the test packet is received by one of the additional devices, the information stored in the additional device includes at least one of (a) the time when a preselected bit in the test packet is received by the additional device and (b) the difference between (i) the time when the preselected bit in the test packet is transmitted from the first device and (ii) the time when the test packet is received by the additional device. The test packet may also be returned from the second device to the first device, or from one of the additional devices to the first device via the same devices traversed by the test packet during transmission from the first device to the one additional device.
The test packet may be transmitted to and from the various devices while normal packets are being transported through the network.
The invention may best be understood by reference to the following description taken in conjunction with the accompanying drawings.
a is a diagrammatic illustration of modified one-way latency measurements for path segments, as well as the entire path, in a packet-based communication network.
a is a diagrammatic illustration of modified two-way latency measurements for path segments, as well as the entire path, in a packet-based communication network.
Although the invention will be described in connection with certain preferred embodiments, it will be understood that the invention is not limited to those particular embodiments. On the contrary, the invention is intended to cover all alternatives, modifications, and equivalent arrangements as may be included within the spirit and scope of the invention as defined by the appended claims.
To allow the tracking of the delays of the individual segments of the end-to-end path of the circuit, a new field is defined within the packet that is used during the test. This new value stores the time stamp created when the first bit of the packet is transmitted for each segmented hop along the end-to-end path. This new value can be used by each device along the path to calculate the delay from the last device to itself, while preserving the information needed to determine the delay in the end-to-end path. This also allows devices that are not aware of this capability to operate normally. The intermediate hop devices can then be interrogated later to easily find the segment delay problem if the end-to-end path has an unacceptable delay measurement.
The first network device to receive the packet 305 along the path 303 is the intermediate device 304. When the test packet 305 arrives at the device 304, the time difference ΔT1 between the time when the last bit is received and the value in the timestamp 307 is calculated and stored in the network device 304. (Alternatively, the timestamp can be taken upon receiving the first bit of the packet 305.) This value ΔT1 is the delay of the path segment from device 301 to device 304. A new timestamp 308, denoting the time when the first bit of the packet 305 is transmitted from the device 304, is taken and stored in the field where the timestamp 307 had been stored.
When the packet 305 arrives at the end-point device 302, the time when the last bit arrives is recorded in the device 302, and the time difference ΔT2 between the timestamp 308 and the recorded time can be stored in the device 302 as the delay of the path segment from device 304 to device 302. The time difference between the arrival time stored in device 302 and the time stored in 306 is the value of the end-to-end delay in the path 303.
a illustrates a modified embodiment of a unidirectional delay measurement made between network devices 301 and 302 along a network path 303 that includes two intermediate network devices 304a and 304b. A test packet 305 is created and transmitted from the first device 301 onto the path 303, and a timestamp 306 is inserted into the packet 305 denoting the time when the first bit of the packet is transmitted from the first device 301.
When the packet 305 arrives at the first intermediate device 304a, the time difference ΔT1 between the time when the last bit is received by the device 304a and the time when the first bit was transmitted from the device 301 (the value in timestamp 306) is calculated and stored in the device 304a. This value ΔT1 is the delay of the path segment from device 301 to device 304a. The test packet 305 is then forwarded to the next network device 304b in the test path.
When the packet 305 arrives at the third device 304b, the time difference ΔT2 between the time when the last bit is received by the device 304b and the time when the first bit was transmitted from the device 301 (the value in timestamp 306) is calculated and stored in the device 304b. Alternatively, the timestamp can be taken upon receiving the first bit of the packet 305. The value ΔT2 is the total delay of the path segments from device 301 to device 304b. The test packet 305 is then forwarded to the last network device 302 in the test path.
When the packet 305 arrives at the final device 302, the time difference ΔT3 between the time when the last bit is received by the device 302 and the time when the first bit was transmitted from the device 301 (the value in timestamp 306) is calculated and stored in the device 302. This value is the total end-to-end delay of the path from device 301 to device 302. The stored time differences ΔT1, ΔT2 and ΔT3 in the respective network devices 304a, 304b and 302 along the test path 303 can then be retrieved centrally by any of several well known techniques for retrieving data from distributed network devices.
In
When the packet 405 arrives at an intermediate network device 404, the time difference ΔT1 between the time when the last bit is received by the device 404 and the value in the timestamp 406 is calculated and stored in the device 404. This value ΔT1 is the delay of the path segment from device 401 to device 404. A new timestamp 407, denoting the time when the first bit of the packet 405 is transmitted from the device 404, replaces the timestamp 406 previously stored in the packet 405.
When the packet 405 arrives at the third device 402, the time when the last bit in the packet 405 arrives at the device 402 is recorded in the device 402 as a timestamp 408. The time difference ΔT2 between timestamp 408 and the time stored in timestamp 407 is calculated and stored in the device 402. This value ΔT2 is the delay of the path segment from device 404 to device 402.
Next, the addresses of the original test packet 405 are reversed in a packet 410 that is transmitted in the reverse direction along the network path 403, from device 402 to device 401 via the intermediate device 404. The packet 410 still contains the original timestamp 415, the recorded timestamp 408 and new timestamps 409 and 411, both denoting the time when the first bit of the packet 410 is transmitted from the device 402.
When the packet 410 arrives at the intermediate network device 404, the time difference ΔT3 between the time when the last bit is received by the device 404 and the value in the timestamp 409 is calculated and stored in the device 404. This value ΔT3 is the delay of the path segment between from device 402 to device 404. A new timestamp 414, denoting the time when the first bit of the packet 415 is transmitted from the device 404 toward the device 401, replaces the timestamp 409 in the packet 410.
When the packet 410 arrives at the third device 401, which is the end point of the return path, the time when the last bit in the packet 410 arrives at the device 401 is recorded in the device 401 as a timestamp 416. The time difference ΔT4 between the recorded time 416 and the time stored in timestamp 414 is calculated and stored in the device 401. This value ΔT4 is the delay of the path segment between from device 404 to device 401.
Also, the difference in time between timestamp 415 and 408 ADDED to the difference in time between timestamp 411 and 416 gives the total round-trip delay of the bi-directional path. An alternative method to calculate the total round-trip delay is to deduct the timestamp 415 from timestamp 416. It is also to be noted that the clocks between the network devices must be precisely synchronized by one of the many methods known to one skilled in the art.
In another embodiment illustrated in
When the packet 405 arrives at the third device 402, the time difference ΔT2 between the time when the last bit is received by the device 402 (stored as timestamp 408) and the time when the first bit was transmitted from the device 401 (the value in timestamp 415) is calculated and stored in the device 402. The value ΔT2 is the total segment delay of the path segment from device 401 to device 402.
Then the addresses of the original test packet 405 are reversed in a packet 410 that is transmitted to the device 401 in the reverse direction along the network path 403. A timestamp 409 is inserted into the packet 410, denoting the time when the first bit of the packet is transmitted from the device 402 onto the return path. Timestamps 415 and 408 are also inserted into the packet. When the packet 410 arrives at the intermediate device 404, the time difference ΔT3 between the time when the last bit is received by the device 404 and the time when the first bit was transmitted from the device 402 (the value in timestamp 409) is calculated and stored in the device 404. This value ΔT3 is the delay of the path segment from device 402 to device 404. The test packet 410 is then forwarded to the network device 401, which is the end point of the path being tested.
When the packet 410 arrives at the device 401, the time difference ΔT4 between the time when the last bit is received by the device 401 (stored as timestamp 416 in device 401) and the time when the first bit was transmitted from the device 402 (the value in timestamp 409) is calculated and stored in the device 401. This value ΔT4 is the delay of the path from device 402 to device 401.
The stored time difference values ΔT1, ΔT2, ΔT3, and ΔT4 stored in the network devices 401, 402 and 404 along the test path can be retrieved centrally. It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrated embodiments and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Also, the difference in time between timestamp 415 and 408 ADDED to the difference in time between timestamp 409 and 416 gives the total round-trip delay of the bi-directional path. An alternative method to calculate the total round-trip delay is to deduct the timestamp 415 from timestamp 416. It is also to be noted that the clocks between the network devices must be precisely synchronized by one of the many methods known to one skilled in the art.
This application is a continuation of and claims priority to U.S. patent application Ser. No. 13/542,449, filed Jul. 5, 2012, now allowed, which is hereby incorporated by reference herein in its entirety.
Number | Name | Date | Kind |
---|---|---|---|
6535983 | McCormack et al. | Mar 2003 | B1 |
6545979 | Poulin | Apr 2003 | B1 |
6604136 | Chang et al. | Aug 2003 | B1 |
6715087 | Vergnaud et al. | Mar 2004 | B1 |
6868094 | Bordonaro et al. | Mar 2005 | B1 |
7113485 | Bruckman | Sep 2006 | B2 |
7114091 | Vrancic | Sep 2006 | B2 |
7242693 | Acharya et al. | Jul 2007 | B1 |
7257123 | Choi et al. | Aug 2007 | B2 |
7281141 | Elkayam et al. | Oct 2007 | B2 |
7283568 | Robie, Jr. et al. | Oct 2007 | B2 |
7286482 | Charcranoon | Oct 2007 | B2 |
7310664 | Merchant et al. | Dec 2007 | B1 |
7463731 | Beyda et al. | Dec 2008 | B2 |
7478251 | Diab et al. | Jan 2009 | B1 |
7519006 | Wing | Apr 2009 | B1 |
7710905 | Dyck et al. | May 2010 | B2 |
7787438 | Dowse | Aug 2010 | B2 |
7873057 | Robitaille et al. | Jan 2011 | B2 |
7936700 | Yamazaki et al. | May 2011 | B2 |
8121111 | Freiberger | Feb 2012 | B2 |
8218576 | Hansson et al. | Jul 2012 | B2 |
8705341 | Robitaille et al. | Apr 2014 | B2 |
20010000071 | Nichols | Mar 2001 | A1 |
20030048754 | Bruckman | Mar 2003 | A1 |
20030048811 | Robie et al. | Mar 2003 | A1 |
20030091029 | Jo et al. | May 2003 | A1 |
20030093513 | Hicks et al. | May 2003 | A1 |
20030115321 | Edmison et al. | Jun 2003 | A1 |
20030115368 | Wu | Jun 2003 | A1 |
20030219025 | Choi et al. | Nov 2003 | A1 |
20040078483 | Simila et al. | Apr 2004 | A1 |
20040105391 | Charcranoon | Jun 2004 | A1 |
20040136713 | Lim et al. | Jul 2004 | A1 |
20040164619 | Parker et al. | Aug 2004 | A1 |
20040165595 | Holmgren et al. | Aug 2004 | A1 |
20050078700 | Thompson et al. | Apr 2005 | A1 |
20050099949 | Mohan et al. | May 2005 | A1 |
20050099951 | Mohan et al. | May 2005 | A1 |
20050099952 | Mohan et al. | May 2005 | A1 |
20050144328 | McBeath | Jun 2005 | A1 |
20050148314 | Taglienti et al. | Jul 2005 | A1 |
20060051088 | Lee et al. | Mar 2006 | A1 |
20070268850 | Hansson et al. | Nov 2007 | A1 |
20070274227 | Rauscher et al. | Nov 2007 | A1 |
20080005354 | Kryskow, Jr. et al. | Jan 2008 | A1 |
20090161569 | Corlett | Jun 2009 | A1 |
20090190482 | Blair | Jul 2009 | A1 |
20100195517 | Kihara | Aug 2010 | A1 |
20100283682 | Heidari-Bateni et al. | Nov 2010 | A1 |
20120134668 | Freiberger | May 2012 | A1 |
20120218879 | Robitaille et al. | Aug 2012 | A1 |
20120257641 | Hansson et al. | Oct 2012 | A1 |
20130010600 | Jocha et al. | Jan 2013 | A1 |
20130170388 | Ito et al. | Jul 2013 | A1 |
20130322255 | Dillon | Dec 2013 | A1 |
20140043992 | Le Pallec et al. | Feb 2014 | A1 |
Number | Date | Country |
---|---|---|
1215559 | Jun 2002 | EP |
S6113414 | Jan 1986 | JP |
S2104339 | May 1987 | JP |
2002-026947 | Jan 2002 | JP |
2003-348119 | Dec 2003 | JP |
2004-200933 | Jul 2004 | JP |
WO 2004040805 | Dec 2004 | WO |
WO 2005025013 | Mar 2005 | WO |
WO 2006033611 | Mar 2006 | WO |
WO 2006114687 | Nov 2006 | WO |
WO 2014006484 | Jan 2014 | WO |
Entry |
---|
Atushi Otha, “Introduction of detail mechanism of Ether OAM,” The Institution of Electronics, Information and Communication Engineers Technical Report, CS2004-79-87 [Communication System], The Institution of Electronics, Information and Communication Engineers, Oct. 21, 2004, vol. 104, No. 380, pp. 35-40. |
De Vito, L. et al. “One-Way Delay Measurement: State of the Art.” IEEE Transactions on Instrumentation and Measurement. vol. 57, No. 12, Dec. 2008, pp. 2742-2750 (9 pages). |
Fasbender, A. et al. “On Assessing Unidirectional Latencies in Packet-Switched Networks.” IEEE International Conference on Communications. vol. 1, Jun. 8, 1997, pp. 490-494 (5 pages). |
Hiroshi Ohta, “Standardization Status on OAM and QoS Issues for Carrier-Class Ethernet,” The Institution of Electronics, Information and Communication Engineers Technical Report, CS2004-79-87 [Communication System], The Institution of Electronics, Information and Communication Engineers, Oct. 21, 2004, vol. 104, No. 380, pp. 29-34. |
International Telecommunication Union, ITU-T, Y.1564, Series Y: Global Information Infrastructure, Internet Protocol Aspects and Next-Generation Networks, Mar. 2011 (38 pages). |
International Telecommunication Union, ITU-T, G.8013/Y.1731, Series G: Transmission Systems and Media, Digital Systems and Networks, Jul. 2011 (92 pages). |
Mills, D. et al. “Network Time Protocol Version 4: Protocol and Algorithms Specification.” Internet Engineering Task Force. Jun. 2010 (220 pages). |
Pezaros, D. et al. “Low-Overhead End-to-End Performance Measurement for Next Generation Networks.” IEEE Transactions on Network and Service Management. vol. 8, No. 1, Mar. 2011, pp. 1-14 (14 pages). |
Time Synchronization in Sensor Networks: A Survey, Sivrikaya et al., Jul.-Aug. 2004 (10 pages). |
Sivrikaya, et al., “Time Synchronization in Sensor Networks: A Survey,” Jul.-Aug. 2004, (10 pages). |
International Search Report and Written Opinion mailed Dec. 6, 2005, which issued in International Patent Application No. PCT/SE2005/001307 (9 pages). |
International Search Report, PCT/IB2006/001000, Nov. 14, 2006 (4 pages). |
International Written Opinion, PCT/IB2006/001000, Nov. 14, 2006 (6 pages). |
European Search Report mailed Sep. 27, 2013, which issued in European Patent Application No. 05779215.2 (6 pages). |
International Search Report and Written Opinion mailed Nov. 25, 2013, which issued in corresponding International Patent Application No. PCT/IB2013/001432 (10 pages). |
Supplementary European Search Report in corresponding European Patent Application No. 06744558.5-1853 (PCT/IB2006/001000), mailed Jul. 17, 2014 (15 pages). |
Number | Date | Country | |
---|---|---|---|
20140341068 A1 | Nov 2014 | US |
Number | Date | Country | |
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Parent | 13542449 | Jul 2012 | US |
Child | 14451763 | US |