1. Technical Field
Embodiments of the present disclosure relate to image decoding technology, and particularly to a method for improving display speed of decoded video bit streams.
2. Description of Related Art
Currently, video bit streams are decoded by a codec to obtain decoded images, and the decoded images are firstly stored in a buffer block of a memory. To play the video, the decoded images have to be moved from the buffer block to a display block of the memory. However, if there are large numbers of decoded images need to be displayed, video playing may be discontinuous and slow while the CPU is kept too busy.
What is needed, therefore, is an improved method for improving display speed of decoding video bit streams.
All of the processes described below may be embodied in, and fully automated by, functional code modules executed by one or more general purpose computers or processors. The code modules may be stored in any type of readable medium or other storage system. Some or all of the methods may alternatively be embodied in specialized hardware. Depending on the embodiment, the readable medium may be a hard disk drive, a compact disc, a digital video disc, or a tape drive.
In some embodiments, the computer 2 is electronically connected to a display device 1, an image capturing device 3, and an input device 4. Depending on the embodiment, the display device 1 may be a liquid crystal display (LCD) or a cathode ray tube (CRT) display, for example.
The computer 2 further includes a storage system 20 to store various information, such as image data 22 captured by the image capturing device 3. In some embodiments, the image capturing device 3 may be an Internet Protocol (IP) camera.
The input device 4 is provided for manually editing an image displayed on the display device 1. In some embodiments, the input device 4 may be a keyboard, or a mouse.
In some embodiments, the decoder 21 includes one or more computerized instructions that are stored in the storage system 20. A processor 23 of the computer 2 executes the computerized instructions to implement one or more operations of the computer 2.
In block S1, the decoder 21 obtains video bit streams (e.g., the image data 22) from the storage system 20. In some embodiments, the video bit streams may be encoded by an H.264 encoder. The decoder 21 may be an H.264 decoder.
In block S2, the decoder 21 decodes the video bit streams in the display block 240 of the memory 24 to obtain decoded images. Detailed descriptions will be given in
In block S3, the decoder 21 selects an image from the decoded images.
In block S4, the decoder 21 updates a reference image stored in the buffer block 242 of the memory 24 with the selected image.
In block S40, the decoder 21 performs an entropy decoding operation on the video bit streams, and then the procedure may go to block S41, S44, or S45 to perform different procedures.
In block S41, the decoder 21 performs a dequantization operation on the video bit streams after performing the entropy decoding operation.
In block S42, the decoder 21 performs an inverse discrete cosine transform operation on the video bit streams after performing the dequantization operation.
In block S43, the decoder 21 performs a rebuilding residual operation on the video bit streams after performing the inverse discrete cosine transform operation, and then the procedure goes to block S47 directly.
In block S44, the decoder 21 performs an intra predicting operation on the video bit streams after performing the entropy decoding operation in block S40, and then the procedure goes to block S46.
In block S45, the decoder 21 reads the reference image from the buffer block 242 of the memory 24, and performs an inter predicting operation on the video bit streams after performing the entropy decoding operation, and then the procedure goes to block S46.
In block S46, the decoder 21 performs an image predicting operation on the video bit streams after performing the intra predicting operation and the inter predicting operation, to obtain predicted images.
In block S47, the decoder 21 performs a rebuilding pixel operation on the predicted images and the video bit streams after performing the rebuilding residual operation.
In block S48, the decoder 21 performs a filtering operation on the predicted images and the video bit streams after performing the rebuilding pixel operation using a deblocking filter, to obtain the decoded images.
In block S49, the decoder 21 outputs the decoded images to the display block 240 of the memory 24.
In some embodiments, the entire blocks of S40-S49 are executed in the display block 240 of the memory 24. In other embodiments, the partial blocks of S45-S49 are executed in the display block 240 of the memory 24, and the other blocks of S40-S44 may be executed in other blocks of the memory 24.
It should be emphasized that the above-described embodiments of the present disclosure, particularly, any embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications may be made to the above-described embodiment(s) of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present disclosure and protected by the following claims.
Number | Date | Country | Kind |
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200910312014.6 | Dec 2009 | CN | national |