Patent Grant
8242702
This Utility Patent Application claims priority to European Patent Application No. EP 08 009 105.1-1239 filed on May 16, 2008, which is incorporated herein by reference.
The present invention relates to a method for driving a fluorescent lamp, in one embodiment for igniting the fluorescent lamp, and a lamp ballast.
Lamp ballasts for fluorescent lamps or gas discharge lamps usually include a half-bridge circuit and a series resonant circuit connected to the half-bridge circuit, which series resonant circuit can be connected to the fluorescent lamp. In this case, the half-bridge circuit serves for exciting the series resonant circuit and for this purpose generates an AC voltage from a DC voltage present across the half-bridge.
A start phase of a lamp ballast includes, for example, a preheating phase and an ignition phase for igniting the lamp. During the preheating phase, incandescent filaments of the lamp are heated by setting a frequency of the AC voltage, which is referred to hereinafter as excitation frequency, in such a way that it lies above the resonant frequency of the series resonant circuit. During the ignition phase, the excitation frequency is increasingly reduced in the direction of the resonant frequency of the resonant circuit, with the aim of increasing a voltage across the fluorescent lamp by using a resonance magnification to an extent such that an ignition voltage of the lamp is obtained and the lamp ignites. During an operating phase after ignition of the lamp, the excitation frequency can then be reduced still further.
During the ignition phase, it should in this case be ensured, on the one hand, that the voltage across the lamp can rise up to the value of the ignition voltage. On the other hand, it should be ensured for safety reasons that the voltage does not rise to an arbitrary extent, for example, when the lamp does not ignite on account of a defect or when no lamp is connected to the resonant circuit. In this respect, U.S. Pat. No. 6,525,492 proposes detecting a current through the half-bridge and immediately switching off the half-bridge if the current exceeds a predetermined threshold value.
For cost reasons, the coil of the resonant circuit is often dimensioned such that it already operates in the vicinity of its magnetic saturation if the lamp voltage lies in the region of the ignition voltage. As is known, the effective inductance of a coil decreases upon transition to the saturation range. If, during the ignition process, an excitation frequency is attained at which the coil begins to go to saturation, then the resonant frequency of the series resonant circuit increases owing to the decreasing inductance of the coil, and a separation between the instantaneous excitation frequency and the resonant frequency decreases. With the excitation frequency remaining constant, the voltage rises further as a result, the coil goes further to saturation and the resonant frequency further approaches the instantaneous excitation frequency. As a result of this positive feedback effect explained, instabilities can arise in the setting of the ignition voltage.
For these and other reasons, there is a need for the present invention.
The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
One embodiment of a method for driving a fluorescent lamp connected to a series resonant circuit including a resonant circuit inductance and a resonant circuit capacitance, includes: applying an excitation AC voltage having an excitation frequency to the series resonant circuit using a half-bridge circuit, having an output, to which the series resonant circuit is coupled, and having a first and a second switch, which are driven in the on state and in the off state with a fundamental (basic) frequency predetermined by a frequency signal or with a lower frequency with respect to the fundamental frequency; detecting a resonant circuit current flowing through the resonant circuit; and driving the switches with the fundamental frequency or with the lower frequency with respect to the fundamental frequency in a manner dependent on a temporal change in the resonant circuit current between two temporally spaced-apart evaluation instants lying within a switched-on duration of one of the switches.
One embodiment of a lamp ballast includes: a series resonant circuit having connection terminals for connecting a fluorescent lamp; a half-bridge circuit having a first and a second switch and having an output, which is connected to the series resonant circuit; a drive circuit, which can assume a first and a second operating state and which is designed to drive first and second switches alternately in the on state and in the off state with a fundamental frequency dependent on a frequency signal or with a lower frequency with respect to the fundamental frequency, and is designed to detect a current through the resonant circuit and, in a manner dependent on a temporal change in the resonant circuit current between two temporally spaced-apart evaluation instants lying within a switched-on duration of one of the switches to drive the switches with the fundamental frequency or with a lower frequency with respect to the fundamental frequency.
In the figures, unless indicated otherwise, identical reference symbols designate identical circuit components and signals with the same meaning.
The lamp ballast additionally includes a half-bridge circuit having a first and a second switch T11, T12, which each have a drive connection and load paths. In this case, the load paths of the switches T11, T12 are connected in series with one another between terminals for a positive supply potential V and a negative supply potential or reference-ground potential GND. The half-bridge circuit has an output OUT, which is formed by a node common to the load paths of the switches T11, T12 and to which the series resonant circuit L1, C1 is coupled. In this case, the series resonant circuit L1, C1 is connected between the output OUT and the terminal for the second supply potential GND. In the example, a coupling capacitor C2 is connected between the output OUT and the series resonant circuit L1, C1, the coupling capacitor serving for blocking DC components in an excitation AC voltage Vout generated by the half-bridge circuit T11, T12 for the series resonant circuit L1, C1.
The half-bridge circuit T11, T12 serves for applying an excitation AC voltage having an excitation frequency to the series resonant circuit. During operation, the switches T11, T12 are for this purpose driven alternately in the on state and in the off state by a drive circuit 1 yet to be explained. When the first switch T11, which is also referred to as high-side switch or upper half-bridge switch, is driven in the on state and the second switch T12, which is also referred to as low-side switch or lower half-bridge switch, is driven in the off state, a voltage corresponding to the supply voltage present between the supply potential terminals is present across the series resonant circuit L1, C1. When the high-side switch T11 is in the off state and the low-side switch T12 is in the on state, the voltage across the series resonant circuit is approximately zero.
In the lamp ballast illustrated in
In one embodiment for reliably avoiding shunt currents, the switches T11, T12 are driven in such a way that a wait during a waiting time, the dead time, is effected between driving one switch in the off state and driving the other switch in the on state. During this dead time, a freewheeling current of the series resonant circuit can be accepted by a freewheeling element, such as a diode D for example, connected in parallel with the low-side switch. When an n-conducting MOSFET is used as the low-side switch, a body diode integrated in the MOSFET can fulfill this freewheeling function, such that an external freewheeling element can be dispensed with.
For driving the switches T11, T12 of the half-bridge circuit, a drive circuit 1 is present, which generates a first drive signal S11 for driving the high-side switch T11 and a second drive signal S12 for driving the low-side switch T12. Driver circuits DRV11, DRV12 are optionally connected upstream of the drive connections of the switches T11, T12, the driver circuits serving for converting signal levels of the drive signals S11, S12 to those signal levels which are suitable for driving the switches T11, T12.
A frequency signal FS is fed to the drive circuit 1, which frequency signal determines the frequency with which the switches T11, T12 are mutually alternately driven, and thus determines the excitation frequency of the series resonant circuit L1, C1. The frequency signal FS is generated for example by a central control circuit, which controls the operation of the lamp ballast, in a manner not illustrated more specifically.
Temporal profiles of the first and second drive signals S11, S12 generated by the drive circuit 1 are illustrated by way of example in
During a drive period, which is designated by Tp in
Between two successive switched-on durations T1, T2 during which one of the drive signals S11, S12 respectively assumes a switch-on level, there is a waiting time, which is referred to hereinafter as dead time, during which both drive signals S11, S12 assume a switch-off level. In
A reduction of the excitation frequency of the AC voltage that excites the resonant circuit L1, C1 in the direction of the resonant frequency brings about an increase in a maximum amplitude value of the current I1 flowing through the series resonant circuit or an AC voltage Vc1 present across the resonant circuit capacitor C1. The temporal profile of the voltage Vc1 follows the temporal profile of the current I1 in a phase-shifted manner. If, with a decreasing excitation frequency, the voltage attains the value of the ignition voltage of the fluorescent lamp LL and the fluorescent lamp ignites, then the excitation frequency can be reduced further down to the value of an operating frequency by using the control circuit 1. After ignition, the energy consumed by the fluorescent lamp is subsequently supplied by using the excitation voltage; in a manner not illustrated more specifically, the current profile is no longer sinusoidal when the fluorescent lamp has been ignited. The reduction of the frequency to the operating frequency after ignition of the fluorescent lamp can be effected by using conventionally known measures, and so further explanations in this respect can be dispensed with.
In order to minimize the material costs for the resonant circuit inductance L1, it is desirable to choose the resonant circuit inductance L1 such that the latter is operated in the region of its magnetic saturation if the resonant circuit current I1 rises up to a value at which the lamp ignites. The feedback effect explained in the introduction can occur in this case.
In order to avoid negative effects of this feedback effect, it is provided that, during an ignition process, that is to say during a time duration during which the fluorescent lamp LL has not yet ignited, the resonant circuit inductance L1 is monitored with regard to an incipient saturation and the switched-on durations of the first and second switches T11, T12 are shortened upon detection of such an incipient saturation. An incipient saturation of the resonant circuit inductance L1 can be detected for example by a comparison of the measurement signal Vs1 proportional to the resonant circuit current I1 with a first and a second threshold value Vr1, Vr2. If the measurement signal Vs1 rises up to the value of the first threshold value Vr1 when the first switch is driven in the on state, then the first switch T11 is switched off directly and before the “normal” switched-on duration dependent on the excitation frequency has actually been attained. If the measurement signal Vs1 attains the value of the lower threshold value Vr2 when the second switch T12 is driven in the on state, then the second switch is switched off directly and before the switched-on duration dependent on the excitation frequency has actually been attained. This leads in each case to shortenings of the switched-on durations of the first and second switches T11, T12 relative to the switched-on durations dependent on the instantaneous excitation frequency. In the case where one of the switches is prematurely switched off owing to saturation as explained, a wait during a dead time Td1′ or Td2′ is effected before the other switch is switched on, where these dead times can be identical in each case and can correspond in one embodiment to the dead times Td1, Td2 during those operating phases in which no premature switching off owing to saturation takes place. A premature switching off of the switches owing to saturation effectively leads to a raising of the excitation frequency and thus counteracts a further resonance magnification and thus a further rising of the voltage in the resonant circuit L1, C1. In one embodiment, the positive feedback effect explained in the introduction is thereby avoided.
The measurement signal Vs1 at least approximately proportional to the resonant circuit current I1 can be generated in various ways.
In the lamp ballast in accordance with
In the method explained above, a premature switching off of the first and second switches T11, T12 upon an incipient saturation of the resonant circuit inductance requires information about the current I1 flowing through the resonant circuit during the entire drive period of the resonant circuit. In this method explained, symmetrical operation of the half-bridge is achieved, that is to say that upon incipient saturation both the switched-on duration of the first switch T11 and the switched-on duration of the second switch T12 are shortened.
A further method for shortening the switched-on duration or for raising the drive frequency, and a lamp ballast having such functionality are explained below.
The lamp ballast illustrated in
The oscillator 6 can assume two different operating states: a first operating state, which is referred to hereinafter as the normal operating state; and a second operating state, which is referred to hereinafter as the saturation operating state. In the normal operating state, the oscillator 6 generates the oscillator signal S6 with a predetermined frequency. This frequency is for example predetermined by the frequency signal FS or dependent on the frequency signal and is referred to hereinafter as the fundamental frequency. This fundamental frequency can change during an ignition process in a manner that has already been explained in principle. In the saturation operating state, the oscillator 6 generates the oscillator signal S6 for a frequency that is higher than the fundamental frequency, in order thereby to counteract the explained positive feedback effect upon an incipient saturation of the resonant circuit inductance L1.
The operating state of the oscillator 6 is dependent on a switched-on duration control signal S7, which is generated by a switched-on duration control circuit 9. In order to generate the switched-on duration control signal S7, the switched-on duration control circuit 9 evaluates a measurement signal Vs2, which is dependent on the resonant circuit current (I1 in
In order to provide the measurement signal Vs2, in the example illustrated, a measuring resistor Rs2 is present, which is connected in series with the switches T11, T12 of the half-bridge and in the example illustrated between the second switch T12 and the lower supply potential or reference-ground potential. It should be pointed out in this context that an upper supply potential of the drive circuit 1 and an upper supply potential of the half-bridge T11, T12 are different. While the upper supply potential of the half-bridge can assume values up to a few hundred volts, the upper supply potential of the drive circuit 1 is in the region of a few volts, for example. By contrast, the lower supply potential of the half-bridge can correspond to the lower supply potential of the drive circuit 1 and can be for example a reference-ground potential, in one embodiment ground.
In the lamp ballast illustrated, the resonant circuit current I1 is measured only during part of the drive period, namely when the second switch T12 is driven in the on state or when a freewheeling diode integrated in the second switch T12 or an external freewheeling diode (not illustrated) is turned on. A temporal profile of a measurement voltage Vs2 present across the measuring resistor Rs2 is illustrated schematically in
One possible realization of the oscillator 6 and one possible realization of the drive signal generating circuit 5 are explained below with reference to
The oscillator 6 illustrated generates a clock signal S6 that alternately assumes a first level, a high level in the example, and a second level, a low level in the example. In the example, the oscillator 6 includes for this purpose a capacitive storage element 61 having a first connection, which is connected to an upper supply potential or positive supply potential via a series circuit including a first current source 62 and a first switch 63 and which is connected to a second supply potential or reference-ground potential via a series circuit including a second current source 64 and a second switch 65. In this case, the upper supply potential can in one embodiment be lower than an upper supply potential of the half-bridge T11, T12.
A second connection of the capacitive storage element 61 which is realized as a capacitor, for example, is connected to the second supply potential in the example. The capacitive storage element 61 is alternately charged via the first series circuit 62, 63 and discharged via the second series circuit 64, 65. In this case, a voltage V61 present across the capacitive storage element 61 has a triangular signal profile, which is illustrated by way of example in
In the case of the oscillator illustrated in
The flip-flop 68 is set and reset in a manner dependent on a comparison of the capacitor voltage V61 with an upper and a lower threshold value V67, V66. In the circuit illustrated, the flip-flop 68 is reset if the capacitor voltage V61 rises up to the upper threshold value V67 when the first switch 63 is driven in the on state, and is set if the capacitor voltage V61 falls to the lower threshold value V66 when the second switch 65 is driven in the on state. In this case, the capacitive voltage V61 and the lower threshold value V66 are fed to a first comparator 66, which has an output connected to the set input of the flip-flop 68. The capacitor voltage V61 and the upper threshold value V67 are correspondingly fed to a second comparator 67, the output of which is fed to the reset input R of the flip-flop 68 via an OR gate 69, yet to be explained. The functioning of this oscillator arrangement 6 is briefly explained below:
If the flip-flop 68 is set, then the first series circuit is activated, whereby the capacitor voltage V61 rises. If the rising capacitor voltage V61 in this case attains the upper threshold value V67, then the flip-flop 68 is reset, whereby the first series circuit 62, 63 is deactivated and the second series circuit 64, 65 is activated. The capacitor 61 is then discharged, whereby the capacitor voltage V61 decreases. If the capacitor voltage V61 in this case attains the lower threshold value V66 then the flip-flop 68 is set again and, as a result, the upper series circuit 62, 63 is activated and the lower series circuit 64, 65 is deactivated. As is illustrated in
In the embodiment illustrated, the drive signal generating circuit 5 includes a delay element 51, to which the clock signal S6 is fed and which generates an output signal S51, which corresponds to the clock signal S6 delayed by a delay duration Td. A temporal profile of the output signal S51 is illustrated in
A dead time between a switch-on level of the first drive signal S11, that is to say driving the first switch T11 in the on state, and a switch-on level of the second drive signal S12 that is to say driving the second switch T12 in the on state, is determined by the delay time Td of the delay element 51 in the drive signal generating circuit 5 illustrated. During this dead time, the clock signal S6 and the delayed clock signal S51 each have mutually complementary signal levels, such that both the first and the second drive signal S11, S12 assume a low level. Dead times between the first switch T11 being turned off and the second switch T12 being turned on and between the second switch T12 being turned off and the first switch T11 being turned on are identical in this drive signal generating circuit 5. The delay element 51 can have a fixedly predetermined delay time, but can also be adjustable with regard to its delay time. In the latter case mentioned, the dead time can be set via the delay element.
In the drive circuit 1 illustrated, the switched-on duration control circuit 9 is designed to generate the switched-on duration control signal S7 upon detection of an incipient saturation of the resonant circuit inductance in such a way that it changes during a drive period from a first signal level, which does not influence the operation of the oscillator 6 to a second signal level. If the switched-on duration control signal assumes the second signal level, then an instantaneous drive period is directly ended or the oscillator is reset before the drive period predetermined by the fundamental frequency has elapsed. In this case, “ending a drive period” or “resetting the oscillator” should be understood to mean that the switch currently in the on state is turned off immediately—only taking account of signal propagation times—in the event of a change in the switched-on duration control signal S7 to the second signal level via the oscillator circuit 6 and the drive signal generating circuit 5. The presence of the second signal level of the switched-on duration control signal S7 thus leads to an increase in the frequency of the oscillator signal S6 and thus to a shortening of the drive period. In the example illustrated, in which the resonant circuit current I1 is evaluated during such a partial period of the drive period Tp in which the resonant circuit current flows through the half-bridge branch with the second switch T12, the switch which is immediately switched off in the event of a change in the switched-on duration control signal S7 to the second signal level is the second switch T12. For the purposes of the explanation below it should be assumed that the first signal level of the switched-on duration control signal S7 is a low level and the second signal level of the switched-on duration control signal S7 is a high level.
In the embodiment illustrated, the switched-on duration control signal S7 is fed to the other input of the OR gate 69, the output of which is connected to the reset input of the flip-flop 68. If the switched-on duration control signal S7 assumes a high level during a drive period, then the flip-flop 68 is reset, whereby the second switch T12 is turned off directly via the inverting output of the flip-flop 68 and the NOR gate 53 of the drive signal generating circuit 5, that is to say before the voltage V61 actually attains the upper threshold value, i.e., before the end of the drive period predetermined by the fundamental frequency has actually been reached. Such a scenario is illustrated in the right-hand part of
If the flip-flop 68 is reset before the triangular voltage signal V61 actually attains the upper threshold value V67 of the oscillator circuit 6, this results in the shortening of not only the time duration of a low level of the clock signal S6 and hence the time duration of driving the second switch T12 in the on state, but also a subsequent discharge duration of the capacitor until the lower threshold value V66 is attained, which is directly apparent on the basis of the temporal profile of the voltage signal V61 in the right-hand part of
In the oscillator 6 illustrated, the capacitor 61 additionally serves for time measurement, namely for determining a time duration between driving the first switch S11 in the off state and an incipient saturation of the resonant circuit inductance L2. This time duration is proportional to the difference between the capacitor voltage V61 at the instant of a switch-off owing to saturation and the lower threshold value V66. Assuming that the triangular signal is generated symmetrically, a discharge duration of the capacitor 61 from this value in the case of switch-off owing to saturation down to the lower threshold value V66 corresponds precisely to the preceding rise duration, whereby a symmetrical driving of the half-bridge switches T11, T12 is also achieved in the case of switch-off owing to saturation, that is to say that a switched-on duration of the second switch T12 before a switch-off owing to saturation corresponds at least approximately to a switched-on duration of the first switch T11 during the subsequent occurrence of the first switch T11 being driven in the on state.
It should be pointed out that the circuit explained with reference to
For the driving of the first and second switches T11, T12, provision is made for generating the drive signals S11, S12 in a manner dependent on the current profile of the current I1 of the series resonant circuit in such a way that one of the switches T11 or T12 remains switched on maximally for a predetermined time duration Tmax after a specific phase angle of the resonant circuit current I1 is present during the switched-on duration of the switch T11 or T12. Such a specific phase angle is attained for example when the resonant circuit current has attained a predetermined current value. This predetermined current value is zero, for example. A switch-off level of the switched-on duration control signal S7 is generated after the time duration Tmax has elapsed after the presence of a specific phase angle, for example a zero crossing. A present drive period is thus ended at the latest after the time duration Tmax has elapsed after the presence of the specific phase angle. If the time duration Tmax ends only after the drive period predetermined by the fundamental frequency has ended, then the switched-on duration control signal S7 has no influence on the oscillator frequency or on the driving of the two switches T11, T12. Such a scenario is illustrated in the left-hand part of
Use is made here of the fact that the phase of the resonant circuit current I1 changes if the resonant circuit inductance starts to go to saturation.
In order to detect those instants at which the resonant circuit current I1 attains a specific phase angle or a predetermined signal level, the switched-on duration controller 9 has a first detection circuit 91, which is designed to compare the current measurement signal Vs2 with a predetermined signal level. A detection signal S91 dependent on a comparison of the current measurement signal Vs2 with the predetermined signal level is available at the output of this first detection circuit. In the example illustrated, the first detection circuit has a comparator having an inverting input and a noninverting input, to which the current measurement signal Vs2 is fed as input signal. In the case of this detection circuit, the detection signal S91 is directly dependent on the sign of the current measurement signal Vs2 and has a first signal level in the case of a positive sign of the current measurement signal Vs2 and a second signal level in the case of a negative sign of the current measurement signal Vs2. In this case, the detection signal S91 is dependent on a comparison of the current measurement signal Vs2 with zero and directly contains information about zero crossings of the current measurement signal Vs2 or of the resonant circuit current I1. The detection circuit S91 is therefore also referred to hereinafter as zero crossing signal, and the first detection circuit 91 as zero crossing detector. In the example illustrated, the comparator is connected up in such a way that the first signal level—present in the case of a negative current measurement signal Vs2—of the detection signal is a high level and the second signal level—present in the case of a positive current measurement signal Vs2—of the detection signal is a low level.
The current measurement signal Vs2, for generating the detection signal S91, can, of course, also be compared with any other fixedly predetermined signal level in order to determine the phase angle of the resonant circuit current I1 or of the current measurement signal Vs2. For this purpose, the current measurement signal Vs2 has to be fed to one of the inputs of the comparator and a reference signal (not illustrated) with the predetermined (comparison) signal level has to be fed to the other of the inputs of the comparator.
The zero crossing signal S91 generated by the zero crossing detector 91 is fed together with the current measurement signal Vs2 to an evaluation circuit 90, which is designed to generate the switched-on duration control signal S7 in a manner dependent on the zero crossing signal S91 and the current measurement signal Vs2 in such a way that the switched-on duration control signal S7 assumes a switch-off level after the time duration Tmax has elapsed after a detected zero crossing of the current measurement signal S7. In this case, in a manner also explained, the time duration Tmax is dependent on the resonant circuit current I1, wherein the current measurement signal Vs2 is used as measurement variable for this resonant circuit current I1 in the example illustrated.
One example of the evaluation circuit 90 is illustrated in
In the embodiment illustrated, the time measurement arrangement 8 has a series circuit including a current source 83 and a capacitive storage element 81, such as e.g., a capacitor, and a switching element 82 connected in parallel with the capacitive storage element 81. In the case of this time measurement arrangement, the time measurement signal V8 corresponds to a voltage across the capacitive storage element 81. This time measurement arrangement 8 can be activated and deactivated via the switching element 82 connected in parallel with the capacitive storage element 81, the switching element being driven by the zero crossing detector 91. In the example illustrated, the time measurement arrangement is activated when the switching element 82 is opened, and is deactivated when the switching element 82 is closed. In the deactivated state, the capacitive storage element 82 is discharged via the switching element 82, such that the time measurement signal V8 is zero in the deactivated state. In the example explained with reference to
To afford a better understanding of the functioning of the evaluation circuit 90 illustrated in
In a manner already explained, a charge state of the capacitor 61 of the oscillator 6 upon the resetting of the flip-flop 68 represents a measure of the switched-on duration of the lower switch T12. The charge state determines the subsequent switched-on duration of the first switch T11, wherein, given identically dimensioned current sources 62, 64 of the oscillator 6 the switched-on duration of the first switch T11 corresponds to the preceding switched-on duration of the second switch T12. A symmetrical driving of the switches T11, T12 of the half-bridge is thereby ensured even though the resonant circuit current I1 is only evaluated during a partial period of the drive period Tp of the half-bridge. In the embodiment explained, the resonant circuit current is evaluated during such a partial period during which the resonant circuit current I1 flows through the branch of the half-bridge with the second switching element T12.
It should be pointed out in this context that the current can, of course, also be evaluated during such partial periods during which the resonant circuit current I1 flows through the branch of the half-bridge with the first switching element T11. An evaluation of the current during the entire drive period is also possible. In this case, in a manner not illustrated, the time measurement arrangement 8 can be activated upon each zero crossing of the current measurement signal Vs2 and the oscillator 6 can be realized, in a manner not illustrated, such that the flip-flop 68 changes its state each time the comparison value V7 is attained by the time measurement signal V8. The above-described property of the oscillator 6 that the time duration from the switch-off of the first switch T11 to the saturation-dictated switch-off of the second switch T12 is equal to the subsequent time duration until the next switch-off of the first switch is not necessary in this case.
In the time profile illustrated in
One embodiment provides for modifying the time measurement arrangement and setting the current supplied by the current source 83 in a manner dependent on the current measurement value Vs2 (illustrated by dashed lines in
Furthermore, there is the possibility of driving the current source of the time measurement arrangement by using the frequency signal FS. In this case, the charging current I83 supplied by the current source 83 is dependent on the frequency signal FS. In this case, the rise time of the time measurement signal V8 until this attains a specific comparison value V7, or the gradient of the time measurement signal V8 over time, is in a fixed relation with respect to the drive period in the normal operating state of the oscillator. The signal range/variation range of the comparison value V7 that is necessary for an ignition voltage control is thereby independent of the resonant frequency of the connected resonant circuit since the rise time of the time measurement signal V8 is virtually normalized to the resonant frequency.
The comparison signal V7 is illustrated as a constant signal in
The method provides for decreasing the comparison value V7 if the current measurement signal Vs2 indicates that a sought voltage amplitude of the oscillation or a sought current gradient of the resonant circuit current has been attained. A shortening of the maximum switched-on duration Tmax is achieved in this way. This shortening of the maximum switched-on duration Tmax can lead to a shortening of the switched-on duration of the second switch T12 and thus subsequently also to a shortening of the switched-on duration of the first switch T11. This is the case particularly when—as illustrated in FIG. 6—upon an incipient saturation of the resonant circuit inductance the instant of the zero crossing is shifted in such a way that after a zero crossing the maximum time duration Tmax has already elapsed before the end of the drive period as predetermined by the fundamental frequency has actually been reached.
The comparison value generating circuit 7 is designed to evaluate the current measurement signal Vs2 at two different instants during a partial period and to determine the comparison signal V7 in a manner dependent on the evaluation results thereby obtained. In this context, a “partial period” should be understood generally to mean a time segment of the drive period Tp during which the current flows through one of the two half-bridge branches. For the purposes of the following explanation it should be assumed that such an evaluation of the current measurement signal Vs2 is effected during such a partial period during which the resonant circuit current flows through the half-bridge branch with the second switch T12. To afford a better understanding,
The current measurement signal Vs2 is evaluated in such a way that a temporal change in the current measurement signal Vs2 from a first evaluation instant t1 to a second evaluation instant t2 is determined. In this case, a temporal change in the current measurement signal Vs2 from the first evaluation instant t1 to a second evaluation instant t2 should be understood to mean a change in the amplitude of the current measurement signal Vs2 relative to the time duration between the first and second evaluation instants, that is to say that the following holds true:
In this case, ΔVs2/Δt designates the temporal change in the current measurement signal Vs2 between the evaluation instants. V1 designates the amplitude value of the current measurement signal Vs2 at the first evaluation instant t1, and V2 designates the amplitude value of the current measurement signal Vs2 at the second evaluation instant t2. Δt designates the temporal spacing between the evaluation instants t1, t2.
For generating the comparison value signal V7, provision is additionally made for comparing the change value ΔVs2/Δt determined during each partial period with a reference value and for generating the comparison signal V7 in such a way that it is dependent on a difference between the change value ΔVs2/Δt and the reference value. One example of a comparison value generating circuit 7 having such a functionality is illustrated in
The change value ΔVs2/Δt can be determined by the sampling circuit 71 in various ways. Referring to
ΔV=|V2−V1| (2)
between the amplitude values V1, V2 determined at the sampling instants t1, t2 directly represents a measure of the change value. In this case, the magnitude of the differences represents a first difference value, from which a second difference value is determined using the reference value Vref in a manner explained. In this case, the comparison value V7 is dependent on a number of second difference values which were determined during a plurality of drive periods. In the case of a steep rise in the current measurement signal Vs2 such as occurs in the case of an incipient saturation of the resonant circuit inductance L1, a larger change value ΔV is obtained in this case than in the case of a less steep rise in the current measurement signal Vs2, such as occurs when the amplitude oscillation is still smaller.
The temporal spacing of the sampling instants t1, t2 is chosen for example such that it is smaller than the time duration between the zero crossing and the instant at which the switch-off level of the switched-on duration control signal S7 is generated. This instant is designated by t7 in
The sampling instants lie in one embodiment sufficiently close to the zero crossing instant such that it is ensured that there is still no saturation of the resonant circuit inductance at the evaluation instants, that is to say that the resonant circuit current present at the evaluation instants is still smaller than a current at which a saturation of the resonant circuit inductance begins. It is ensured in this way that an evaluation of the resonant circuit current for determining the oscillation amplitude is effected at a time at which there is still no saturation-dictated distortion of the current profile.
Referring to
The generation of the change value ΔVs2/Δt and the generation of the comparison signal V7 are coordinated with one another in such a way that the comparison value V7 becomes all the smaller, the larger the change value ΔVs2/Δt becomes in comparison with the reference value Vref. A large change value ΔVs2/Δt indicates a steep signal profile of the current measurement signal Vs2; in this case, the maximum time duration Tmax during which the second switch T12 still remains switched on after the zero crossing of the current measurement signal Vs2 is to be reduced in order to reliably prevent very high current values of the resonant circuit current I1 from being attained.
In the case of the explained generation of the comparison signal V7 using a sampling circuit 71 and a controller 72, changes in the temporal profile of the current measurement signal Vs2 affect the generation of the comparison signal V7 only in time-delayed fashion with a delay time of one period duration. In order, at the beginning of saturation operation of the resonant circuit inductance L2, directly to achieve a shortening of the drive period Tp and thus an increase in the switching frequency, in one example provision is made for generating the time measurement signal V8 in a manner dependent on the resonant circuit current I1 in such a way that the time measurement signal V8 rises more rapidly at a high resonant circuit current I1, such that with the comparison value V7 initially unchanged, the comparison value V7 is nevertheless attained earlier.
Referring to
As an alternative or in addition to the provision of such a coupling capacitor 84, there is the possibility of realizing the current source 83 of the time measurement arrangement 8 in such a way that this generates the charging current I83 for the capacitive storage element 81 in such a way that the charging current 83 rises if the current measurement signal Vs2 exceeds a predetermined threshold value. Such a dependence of the charging current I83 on the current measurement signal Vs2 is illustrated by way of example in
In one embodiment of a circuitry realization of a controlled current source 83 having the functionality explained with reference to
The controlled current source 83 additionally has a comparator 833, 834, which compares the current measurement signal Vs2 with the threshold value Vth and which, depending on this comparison result, adds to the fundamental current I831 supplied by the first current source 831 a part of the current I832 supplied by the second current source 832, which part is dependent on the comparison. The comparator has two transistors 833, 834, of which a first 833 is driven by the current measurement signal Vs2 and of which a second 834 is driven by a voltage source 839 that provides the threshold value Vth. In this case, the load path of the first transistor 833 is connected between the second current source 832 and a reference-ground potential, while the load path of the second transistor 834 is connected between the second current source 832 and the node common to the two transistors 835, 836 of the first current mirror. In the example illustrated, the two transistors 833, 834 of the comparator circuit are realized as p-channel transistors. If the current measurement signal Vs2 is less than the threshold value Vth, then the first transistor 833 of the comparator circuit conducts more than the second transistor 834, with the result that a significant part of the second current I832 flows away via the first transistor 833. If the current measurement signal Vs2 exceeds the threshold value Vth, then a significant part of the current I832 flows via the second transistor 834 and in this way is fed into the first current mirror and thus contributes to an increase in the charging current I83.
A comparison value generating circuit 7 which is simple and can be realized cost-effectively, and which generates the comparison value V7 in a manner dependent on the change value in the manner explained, is illustrated in
The comparison value generating circuit 7 has the already explained controller 72 having an inverting input and a noninverting input and an output, at which the comparison value V7 is available. In the example illustrated, the controller 72 has a control amplifier 721 and also two capacitances 722, 723, which are connected in parallel with one another between the inverting input and the output of the control amplifier 721. In this case, a switch 724 is connected in series with one 723 of the two capacitances 722, 723. A voltage source 80 is connected between the noninverting input of the control amplifier 721 and a reference-ground potential GND, which voltage source provides a constant voltage and serves for setting the operating point of the controller 72. The control amplifier 721 is embodied as an operational amplifier and is in this case connected up to the capacitance 722 as an integrator that integrates the charge available at its inverting input.
The comparison value generating circuit 7 additionally has a first capacitance 74 and a second capacitance 75, which each have first and second connections and the second connections of which are connected to a common circuit node. This common circuit node is connected via a first switch 78 to the noninverting input and via a second switch 79 to the inverting input of the controller 72. The first connection of the first capacitance 74 can optionally be connected to the reference voltage source 73, which provides the reference signal Vref, or reference-ground potential GND via two further switches: a third switch 76 and a fourth switch 77. The current measurement signal Vs2 is fed to the first connection of the second capacitance 75.
During a drive period, the comparison value generating circuit 7 has three different operating states, which are designated by A, B and C. The individual switches of the comparison value generating circuit 7 are driven in the on state or in the off state during these operating states. In order to afford a better understanding,
A first operating state or a first operating phase A extends up to the first evaluation instant t1, which for example coincides with the zero crossing instant. During this operating phase, the first switch 78 and the third switch 76, which connects the first capacitance 74 to the reference voltage source 73, are closed. The first capacitance 74 is thereby charged to a voltage which corresponds to the reference voltage Vref minus the operating point voltage V80 supplied by the voltage source 80. During this operating phase, a voltage corresponding to the current measurement signal Vs2 minus the operating point voltage V80 is present across the second capacitance 75.
The second operating state or the second operating phase B begins with the first evaluation instant t1 and ends with the second evaluation instant t2. At the instant t1, the first switch 78 is opened and the second switch 79 is closed. In addition, the third switch 76, which connects the first capacitance 74 to the reference voltage source 73, is opened, and the fourth switch 77, which connects the first capacitance 74 to reference-ground potential GND, is closed. The first evaluation instant corresponds for example to the zero crossing instant, this being taken as a basis for the following explanation. For the following explanation of the processes during the second operating phase B it should be assumed that the current measurement signal Vs2 changes slowly after the zero crossing instant relative to the duration of the also explained switching processes of the switches 76-79 and relative to the duration of a settling process—yet to be explained—of the operational amplifier 721, with the result that the influence of a change in the current measurement signal Vs2 at the beginning of the operating phase B can initially be disregarded.
If the second switch 79 is closed at the beginning of the second operating phase, then the integrator 721, 722 integrates all the charges fed in to its inverting input. Shortly before the first sampling instant t1, that is to say shortly before the closing of the second switch 79, the voltage across the second switch 79 is zero. This is due to the fact that the first switch 78, which is closed during the first operating phase, constrains the potential of the common node of the first and second capacitances 74 and 75 to the value of the operating point voltage V80 and that the differential input voltage of the control amplifier 721, which is realized as an operational amplifier, is zero when the control loop is closed. If, at the first sampling instant t1, the first switch 78 is opened and the second switch 79 is closed, as a result of this process alone no charge flows toward the inverting input or away from the inverting input. At the same time, however, the third switch 76 is opened and the fourth switch 77 is closed. As a result of this process, the potential at the common node of the first capacitance 74 and of the first and second switches 76, 77 changes by a voltage corresponding to the reference voltage Vref. Since the operational amplifier 721 reestablishes the voltage balancing at its inputs on account of the closed control loop, the potential at the node common to the first capacitance 74 and second switch 79 is identical before the beginning of the second operating phase, that is to say before the first sampling instant t1, and after the elapsing of a settling time of the operational amplifier 721 after the beginning of the second operating phase. In this case, the electrical charge stored in the first capacitance 74 changes by a value corresponding to the product of the capacitance value of the first capacitance and the reference value Vref. In the course of the settling process, this quantity of charge flows away from the inverting input of the operational amplifier 721 and thus from the integrator input. In this case, the voltage at the output of the integrator changes by a voltage difference corresponding to the quotient of the quantity of charge that has flowed away and the capacitance value of the capacitance Z2 of the controller 7. This change can be seen in the temporal profile in accordance with
In the further temporal course of the second operating phase, the current measurement signal Vs2 slowly rises further. One connection of the second capacitance 75 is fixedly at the value of the current measurement signal Vs2, while the other connection is connected via the still closed second switch 79 to the integrator input, that is to say the noninverting input of the control amplifier 721, and is at a constant potential corresponding to the operating point voltage V80. In the further course, a change in the voltage across the second capacitance 75 corresponds to a temporal change in the current measurement signal Vs2. In this case, overall a charge corresponding to the voltage change in the current measurement signal Vs2 starting from the instant t1 multiplied by a capacitance value C75 of the second capacitance 75 flows to the integrator input.
At the second sampling instant t2, the second switch 79 is opened again and the first switch 78 is closed. Starting from this instant, therefore, no further charge can flow from the second capacitance 75 toward the integrator input or away from the latter, the integrator state is as it were frozen. The voltage change at the integrator output from an instant after the first sampling instant t1 at which the operational amplifier 721 has settled until the second sampling instant t2 corresponds to the voltage change in the current measurement signal Vs2 within this time negatively multiplied by the capacitance ratio C75/C722 of the capacitance values C75 and C722 of the second capacitance 75 and, respectively, the capacitance 722 of the integrator. From the instant t1 until the settling of the operational amplifier, the integrator output changes by the value of the reference voltage Vref multiplied by the capacitance value C74/C722 of the capacitance values C74 and C722 of the first capacitance 74 and the capacitance C722 of the integrator. Thus, a voltage change ΔV7 at the integrator output from the first sampling instant t1 until the second sampling instant t2 amounts overall to
If the following holds true for the change ΔV in the current measurement signal Vs2 within the evaluation time period Δt lying between the two sampling instants:
then there is no change in the comparison value V7 relative to the sampling instants t1, t2. The value given by Vref·C74/C75 in this case represents a reference value with which the change ΔV in the current measurement signal Vs2 is compared in order to generate the comparison signal V7. If the change ΔV in the current measurement signal Vs2 is less than this reference value, then the comparison signal V7 rises relative to the sampling instants; the time profile for this case is illustrated as a dashed line in
The comparison signal V7 available at the output of the integrator remains frozen after the end of the second operating phase during the third operating phase C until the switch-off instant t7 and is used in accordance with the explanations above for generating the switched-on duration control signal S7.
The third operating phase can end at the instant t7 or later. This third operating phase is followed by a new first operating phase A. When the operating phase transition from the third to the first phase takes place is irrelevant; it should take place during the switched-off duration of the switch T12. In the operating phase A, a further capacitance 723 is connected in parallel with the capacitance 722 of the integrator. The capacitance value of the capacitance 723 is for example approximately three to ten times the capacitance value of the capacitance 722. The capacitance 723 is charged during the first operating phase A to a voltage value corresponding to the difference between the comparison signal V7 at the output of the integrator and the operating point voltage V80. In the succeeding operating phase C, a voltage corresponding to the difference between the “new” comparison signal V7 and the operating point voltage V80 is present across the capacitance 722 of the integrator. As a result of the parallel connection during the subsequent operating phase A, the voltages across both capacitances become matched to a value corresponding to an average value of the voltage during the preceding operating phase A and the directly preceding operating phase C, weighted according to the capacitance ratio of the capacitances 722 and 723.
The deviations of the temporal change ΔV in the current measurement signal from the reference value Vref·C74/C75 are summed for all preceding cycles in the form of the charge of the capacitance 723. The charge stored in this capacitance 723 thus represents the integral component (I component) of the signal present at the output of the controller. The pure I component can be tapped off at the integrator output V7 during the operating phases A. Since the charge of the capacitance 722 is reset to the I component during each operating phase A, but until the operating phase C additionally experiences a charge change proportional to the deviation of the temporal ΔV from the reference value Vref·C74/C75 of the respective operating cycle, the capacitance 722 contains during the operating phase C a charge that differs from the I component by a proportional component (P component). The ratio of I component and P component can be selected by using the capacitance ratio of the capacitances 722 and 723. The sum of I component and P component of the controller output voltage can be tapped off as comparison signal V7 during the third operating phases C. Expressed in a highly simplified way, the capacitance ratio of the capacitances is a measure of how often the capacitance 722 has to be charged during the operating phase B to a voltage that is different with respect to the capacitance 723, and subsequently has to be discharged into the capacitance 723 during the operating phase A until the voltage at the capacitance 723 changes by as much as the voltage of the capacitance 722 changes during each operating phase B.
Referring to
The individual switches are controlled by a sequence controller (not illustrated in greater detail). By way of example, information about the instant of the zero crossing is fed to the sequence controller. Information about the evaluation duration Δt=t2−t1 is for example fixedly programmed in the sequence controller, such that the start and end of the second operating phase B and hence the end of the first and the start of the third operating phase are fixed taking account of the zero crossing instant. The sequence controller additionally requires information about the switch-off instant at which the second switch T12 is switched off, and is designed for example to choose the end of the third operating phase—and hence the start of the subsequent first operating phase—in such a way that it lies a predetermined time duration after the switch-off instant.
In the case of the ballast illustrated, a reduction of the comparison voltage V7 brings about a shortening of the maximum switched-on duration, which, particularly when the resonant circuit inductance is operated in the region of its saturation, can lead to an increase in the excitation frequency since the switched-on duration of the lower switch T12 is shortened starting from the zero crossing. The oscillation amplitude of Vs2 decreases as a result. Conversely, a raising of the comparison voltage V7 brings about a lengthening of the maximum switched-on duration Tmax, which can lead to a reduction of the excitation frequency and hence to an increase in the oscillation amplitude for as long as the oscillator is in the saturation operating state. In the normal operating state, by contrast, the excitation frequency and the oscillation amplitude are independent of the comparison voltage V7 since the end of the switched-on duration of the second switch is already attained in this case before the oscillator is actually reset by the switched-on duration control signal S7.
Referring to the explanations above, the comparison signal V7 influences the switching frequency of the half-bridge only when the time measurement signal V8 attains the value of the comparison signal V7, before the end of the switched-on duration—predetermined by the fundamental frequency of the oscillator 6—of the second switch T12 has actually been reached. In order to ensure that the drive circuit reacts rapidly upon an incipient saturation of the resonant circuit inductance, that is to say that the comparison signal V7 is rapidly decreased, in order effectively to achieve a shortening of the drive period, one embodiment provides for already generating the comparison signal V7 during the time duration during which the frequency signal FS is decreased for the ignition of the lamp such that the switched-on duration predetermined by the switched-on duration controller 9 approximately corresponds to the switched-on duration predetermined by the fundamental frequency of the oscillator 6. This is tantamount to generating the comparison signal V7 such that the time measurement signal V8 attains the comparison signal V7 at the same instant at which the voltage across the capacitor 61 of the oscillator 6 attains the upper comparison value V67. In this case, the comparison value signal V7 initially has no influence on the drive frequency. However, if the resonant circuit inductance starts to go to saturation, and if the resonant circuit current rises rapidly, then the comparison value V7 can be rapidly reduced further proceeding from the “settled value” established previously, in order thereby more effectively to limit the switched-on durations of the two switches of the half-bridge and hence initially to raise the drive frequency again.
The functioning of the ballast explained is explained below with reference to
The amplitude of the current measurement signal Vs2 initially rises relatively slowly during the reduction of the frequency f. The comparison signal V7 can be tracked during this phase in such a way that the oscillator 6 is operated in the normal operating state but at the limit with respect to the saturation operating state. The comparison signal V7 is therefore set in such a way that a signal pulse of the switched-on duration control signal S7 (cf.
In
During the rise in the current amplitude, the excitation frequency f increases owing to the shortening of the switched-on durations. This increased frequency lies for example in the region of 50 kHz. The oscillator then operates in the saturation operating state, that is to say that the switched-on duration control signal S7 determines the excitation frequency, and not the frequency signal FS any longer. This transition of the oscillator 6 into the saturation operating state is detected by the sequence controller (not illustrated), which thereupon does not reduce the frequency signal further. Such a detection of the saturation operating state can be effected, referring to
The above-explained control of the comparison signal V7, for example by using a P1 controller, prevents an uncontrolled rise in the resonant circuit amplitude during this operating state. In the example illustrated, a rise in the comparison signal V7 after the saturation instant ts can be explained by the fact that the rate of current rise or the determined temporal change ΔV in the current measurement signal Vs2 at this instant still lies below the desired value/reference value. As a result, the oscillation amplitude still increases until an instant tmax_am, at which the temporal change ΔV in the current measurement signal Vs2 attains the reference value, such that no further rise in the comparison value V7 takes place any more. If the comparison signal were not readjusted at the limit between normal operating state and saturation operating state, the comparison signal would be virtually constant until the beginning of the saturation operating state.
In
In
The above-explained method for controlling the ignition voltage operates very stably and accurately in the case of a constant load or in the case of a slowly changing load. In one embodiment, even lamp circuits with current preheating, in which the lamp takes up a very high active power for the heating filaments connected in series with the resonance capacitor, can be controlled sufficiently accurately. Particularly in the case of cold start devices, in which the lamp is not preheated by the ignition, it can happen, however, that firstly a corona discharge of the lamp commences and the lamp in this case takes up active power, to which the ignition controller reacts by raising the comparison value V7 in order to provide the active power consumed. However, the corona discharge can spontaneously also cease occasionally, whereby the oscillation amplitude of the resonant circuit current I1 rises relatively rapidly owing to the high active power provided. For stability reasons, however, the controller 72 of the evaluation circuit is dimensioned in such a way that it cannot react rapidly enough to such a very rapid rise. In this case, a shutdown will occur owing to overcurrent by using an overcurrent protection circuit (not illustrated in more specific detail) present in the half-bridge.
In order to avoid such a switch-off owing to overcurrent, one embodiment provides for evaluating the input signal of the controller 72 or the proportional component of the comparison signal V7 independently of the integral component and, in the case of a rapid rise in the proportional component, reducing the comparison signal V7 abruptly to a small value, to be precise to such a value which is usually established without an active-power load. From this new start value of the comparison value V7, the oscillation amplitude cannot at least rapidly rise further and the controller 72 has time to settle again under the changed load conditions. Such a process is illustrated in
In the case of a strong saturation of the resonant circuit inductance, the profile of the resonant circuit voltage changes from a sinusoidal profile to a trapezoidal profile. In this case, the root-mean-square value, which is critical for ignition of the lamp, is higher for the same amplitude in the case of a trapezoidal voltage profile than in the case of a sinusoidal voltage profile. One embodiment provides, then, for detecting the saturation depth, that is to say for detecting how strongly the resonant circuit inductance is operated in saturation. This can be done for example by evaluating the peak current or the maximum value of the current measurement signal Vs2. In this case, the saturation depth is all the higher, the higher the maximum value. In the case of a high saturation depth and a trapezoidal voltage profile resulting therefrom, provision is made for reducing the oscillation amplitude established under the control of the comparison signal V7 during the saturation operating state. This is done, for example, by a comparison signal being generated in a manner dependent on the saturation depth and being reduced in the case of a high saturation depth. This can be done, in the case of the controller 7 illustrated in
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
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