This application incorporates by reference Taiwan application Serial No. 090130455, filed Dec. 7, 2001.
1. Field of the Invention
The invention relates in general to a method for driving a plasma display panel (PDP) and structure thereof, and in particular, to a method for driving a PDP having a priming electrode and structure thereof
2. Description of the Related Art
As the fabrication technology of the audio/video (A/V) devices is developing rapidly, higher quality audio and video services are foreseen popular among the users. Take the display device for example. The conventional cathode ray tube (CRT) display cannot provide better audio and video quality than movies, as well as having the disadvantages of large volume, serious radiation issue, and serious image contortion and distortion at the brim region of the screen. The conventional CRT display device certainly cannot satisfy the demands for higher quality audio and video services When the high definition digital television (HDTV) begins to broadcast and the compliant products become more affordable, the CRT displays will be phased out. The plasma display panel (PDP) display, with the advantages of low radiation, low power consumption, and large display area with small volume, will be a very promising HDTV display to replace the CRT display.
A plurality of address electrodes A are formed on the rear substrate 108, and are orthogonal to the sustaining electrodes X and the scanning electrodes Y respectively. The address electrodes A are covered with a dielectric layer 116. A plurality of ribs 112 are formed on the dielectric layer 116 and are parallel to the address electrodes A. A fluorescence layer 110 is formed between the adjacent ribs 112 and on the sidewall of the ribs 112.
A black matrix 212 on the front substrate 102 is positioned between each pair of driving electrodes, and is also in the dark area 203. The black matrix 212 is opaque and is used for blocking the light from the exterior environment so as to increase the contrast of the PDP. The space between the front substrate 102 and the rear substrate 108 is called a discharge space 214 and is filled with the discharge gas mixed with Ne and Xe.
Each pixel unit 200 can be regarded as a capacitive load. The driving circuit provides the alternating current of high frequency for charging each pixel unit 200 through the corresponding sustain electrode X and scan electrode Y The gas in the discharge space 214 is excited, discharged, and then emit UV light. The fluorescence layer 110 absorbs the UV light of specified wavelengths and then emits visible lights.
In the address period T2, the image data signals are applied to the pixel units, which are selected to emit lights. In the sustain period T3, light pulses are produced by applying alternating voltages across the sustain electrode X and the scan electrode Y of the selected pixel units by the help of the memory effect of the wall charges.
The reset period T1 further includes three periods: a first reset period T11, a second reset period T12, and a third reset period T13. During the first reset period T11, a first erase pulse PY1 of about 100 μs duration is applied to all the scan electrodes Y so as to remove the wall charges remaining after the last sustain period. During the second reset period T12, a priming pulse PX2 is applied to all the sustain electrodes X so as to produce wall charges on the pixel units again and so as to reset the status of the wall charges to be the same. Since the priming pulse PX2 provides an instant high voltage across the sustain electrode X and scan electrodes Y, the discharge gas in the discharging space 214 is excited, and becomes the wall charges in each pixel unit. During the third reset period T13, a second erase pulse PY3 of about 100 μs duration is applied to the all scan electrodes Y to remove the redundant wall charges in each pixel unit. Another pulse can be applied to the sustain electrode X in order to remove the wall charges remaining after the last sustain period and the discharge ion remaining in this driving sequence respectively during the first reset period T11 and the third reset period T13.
During the second reset period T12, there are two ways to provide a priming pulse PX2. The first one is to provide a priming pulse PX2 of high level voltage and of positive polarity to the sustaining electrode X as shown in
However, the discharge ion induces the fluorescence layer 110 emitting visible light, which is called as the background glow. The background glow during the reset period T1 will decrease the contrast ratio of the PDP, and lower the quality of the PDP.
It is therefore an object of the invention to provide a plasma display panel (PDP) with improved the contrast ration, the quality, and the lifetime thereof, wherein a quantity of discharge ions is produced during a reset period.
The present invention discloses a PDP with a priming electrode. The PDP has a first substrate and a second substrate opposite to each other, wherein the space between the first substrate and the second substrate is defined as a discharge space and is filled with a discharge gas. The PDP is divided into a pixel unit and a dark area and comprises a sustaining electrode, a scanning electrode, a priming electrode, and an address electrode. The sustaining electrode and the scanning electrode are positioned in the pixel unit on the first substrate along a first direction, and the address electrode is positioned on the second substrate perpendicularly with the first direction. The priming electrode is positioned in the dark area on the first substrate along the first direction and outputs a first priming pulse so as to excite the discharge gas and to produce a plurality of discharge ions.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings in which:
The present invention installs a priming electrode in the dark area so as to excite the discharge gas and to produce the discharge ion by providing a priming pulse in the reset period.
During the first reset period T11, an erase pulse PY1 of about 100 μs duration is applied to all the scan electrodes Y so as to remove the wall charges remaining after the last sustain period by the voltage difference between the scan electrode Y and the sustain electrode X. During the second reset period T12, a priming pulse PP is applied to all the priming electrodes P so as to produce wall charges in the discharging space 414 by the voltage difference between the priming electrode P and the address electrode. The voltage of the priming pulse PP is larger than that of the erase pulse PY1. During the third reset period T13, a erase pulse PY3 of about 100 μs duration is applied to the all scan electrodes Y to remove the redundant wall charges in each pixel unit 400 by the voltage difference between the scanning electrode and the sustaining electrode. The erase pulse PY1 and the erase pulse PY3 can be positive or negative polarity, as well as the priming pulse PP.
The priming electrode P of the present invention is only used for applying priming pulse during the second reset period T12. Since the priming electrode P is positioned in the dark area 403, the produced discharge ion is also concentrated near the dark area 403. The visible light from the fluorescence layer 413b is blocked by the black matrix 412, and the background glow received by the user becomes less. Thus, the contrast ratio of the PDP is improved, as well as the quality thereof. Moreover, the UV light emitted from the discharge ion principally illuminates the fluorescence layer 413b in the dark area 403, but not the fluorescence layer 413a in the pixel unit 400. Thus, the lifetime of the fluorescence layer 413a in the pixel unit 400 is increased, as well as the fluorescence layer 413.
In
Other than the advantages described in FIG. SA and
From the above description, the present invention improves the contrast ration, the quality, and the lifetime of the PDP by applying a priming electrode in the dark area. Moreover, the driving sequence and the driving circuit of the present invention are simplified, and the power consumption is decreased.
While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Number | Date | Country | Kind |
---|---|---|---|
90130455 A | Dec 2001 | TW | national |
Number | Name | Date | Kind |
---|---|---|---|
5969478 | Shino et al. | Oct 1999 | A |
6144348 | Kanazawa et al. | Nov 2000 | A |
6150766 | Shino et al. | Nov 2000 | A |
6271810 | Yoo et al. | Aug 2001 | B1 |
6476562 | Yoo et al. | Nov 2002 | B1 |
6605897 | Yoo | Aug 2003 | B1 |
6816135 | Ide et al. | Nov 2004 | B1 |
20010026254 | Ide et al. | Oct 2001 | A1 |
20040056606 | Ide et al. | Mar 2004 | A1 |
Number | Date | Country |
---|---|---|
09-245627 | Sep 1997 | JP |
Number | Date | Country | |
---|---|---|---|
20030107533 A1 | Jun 2003 | US |