Method for driving a plasma display panel

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for driving a plasma display panel (hereinafter, simply referred to as PDP) of a matrix display scheme.

2. Description of the Related Art

In recent years, in association with the enlargement of a display apparatus, a thin type display apparatus has been requested and various thin type display apparatuses have been put into practical use. An AC (alternate current discharge) type PDP is highlighted as one type of the thin display apparatuses.

The PDP has a plurality of column electrodes (address electrodes) and a plurality of row electrodes arranged so as to cross the column electrodes. Each of the row electrode pairs and the column electrodes are covered with a dielectric material layer against a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed at a cross point of the row electrode pair and the column electrode. Since the PDP performs a light emission display by using a discharge phenomenon, each of the discharge cells has only two states: namely, a state where it emits the light and a state where it does not emit the light. A sub-field method is, therefore, used to realize a halftone luminance display corresponding to an input video signal by the PDP. According to the sub-field method, a display period of one field is divided into N sub-fields, the number of light emission times corresponding to a weight of a bit digit of pixel data (N bits) according to the input video signal is allocated to each sub-field, and the light emission driving is executed.

When a jitter occurs in a vertical sync signal in the input video signal, however, there is a case where a display period of one field becomes short. In this instance, all of the N sub-fields cannot be executed within the short 1-field display period. When the video signal in which the jitter occurred in the vertical sync signal is supplied, therefore, a desired gradation luminance cannot be obtained and there is a problem of deterioration of a display image quality.

OBJECTS AND SUMMARY OF THE INVENTION

The invention is made to solve the problems and it is an object of the invention to provide a method for driving a plasma display panel in which even if a video signal having a jitter is supplied, a preferable image display is performed.

According to the invention, there is provided a method for driving a plasma display panel having discharge cells each corresponding to one pixel formed at each of intersecting points between a plurality of row electrodes arranged at respective scanning lines and a plurality of column electrodes intersecting said row electrodes, comprising the steps of: executing, in each of a plurality of sub-fields forming a display period of one field of an input video signal, a pixel data writing step and a light emission sustaining step, said pixel data writing step being to set each of said discharge cells to one of a light emitting cell and a non-light emitting cell in accordance with a pixel data based on said input video signal, said light emission sustaining step being to allow only said light emitting cells to perform a light emission by a number of times corresponding to a weight of said sub-field, in which at least one of an execution time of said pixel data writing step in each of said sub-fields, an execution time of said light emission sustaining step in each of said sub-fields, and the number of sub-fields within said display period of one field is adjusted in accordance with a jitter of a vertical sync signal in said input video signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a diagram showing a schematic construction of a plasma display apparatus for light emission driving a PDP

10

on the basis of a driving method according to the invention;

FIGS. 2A and 2B

are diagrams showing an example of a light emission driving format based on the driving method according to the invention;

FIG. 3

is a diagram showing applying timings of various driving pulses which are applied to the PDP

10

in one sub-field;

FIG. 4

is a diagram for explaining the light emission driving operation in the plasma display apparatus shown in

FIG. 1

;

FIGS. 5A and 5B

are diagrams showing another example of a light emission driving format based on the driving method according to the invention;

FIGS. 6A and 6B

are diagrams showing another example of a light emission driving format based on the driving method according to the invention;

FIG. 7

is a diagram showing a light emission driving format at the time of a gradation driving in which a resetting step Rc is executed only once during a 1-field period;

FIG. 8

is a diagram showing another construction of a plasma display apparatus for light emission driving a PDP

10

on the basis of a driving method according to the invention;

FIG. 9

is a diagram showing an internal construction of a data converting circuit

30

;

FIG. 10

is a diagram showing converting characteristics in a first data converting circuit

32

;

FIG. 11

is a diagram showing an example of a conversion table in the first data converting circuit

32

;

FIG. 12

is a diagram showing an example of a conversion table in the first data converting circuit

32

;

FIG. 13

is a diagram showing an internal construction of a multi-gradation processing circuit

33

;

FIG. 14

is a diagram for explaining the operation of an error diffusion processing circuit

330

;

FIG. 15

is a diagram showing an internal construction of a dither processing circuit

350

;

FIG. 16

is a diagram for explaining the operation of the dither processing circuit

350

;

FIG. 17

is a diagram showing all patterns of the light emission driving which is executed on the basis of the light emission driving format shown in

FIG. 7

;

FIGS. 18A and 18B

are diagrams showing an example of a light emission driving format which is used in the plasma display apparatus shown in

FIG. 8

;

FIG. 19

is a diagram showing applying timings of various driving pulses which are applied to the PDP

10

of the plasma display apparatus shown in

FIG. 8

;

FIG. 20

is a diagram showing all patterns of the light emission driving which is executed on the basis of the light emission driving format shown in

FIGS. 18A and 18B

;

FIGS. 21A and 21B

are diagrams showing another example of a light emission driving format which is used in the plasma display apparatus shown in

FIG. 8

;

FIGS. 22A and 22B

are diagrams showing another example of a light emission driving format which is used in the plasma display apparatus shown in

FIG. 8

; and

FIG. 23

is a diagram showing another example of all patterns of the light emission driving which is executed on the basis of the light emission driving format shown in

FIGS. 18A and 18B

.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will now be described hereinbelow with reference to the drawings.

FIG. 1

is a diagram showing a schematic construction of a plasma display apparatus for light emission driving a plasma display panel on the basis of a driving method according to the invention.

As shown in

FIG. 1

, the plasma display apparatus is constructed by: a PDP

10

as a plasma display panel; and a driving unit comprising an A/D converter

1

, a drive control circuit

2

, a sync detecting circuit

3

, a memory

4

, a jitter detecting circuit

5

, an address driver

6

, a first sustain driver

7

, and a second sustain driver

8

.

The PDP

10

has: m column electrodes D

1

to D

m

serving as address electrodes; and n row electrodes X

1

to X

n

and n row electrodes Y

1

to Y

n

arranged so as to cross the column electrodes, respectively. In this instance, the row electrodes corresponding to one row in the PDP

10

are formed by pairs of row electrodes X and row electrodes Y. The column electrodes D and the row electrodes X and Y are covered with a dielectric material layer against a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed at a cross point of each row electrode pair and the column electrode.

The A/D converter

1

samples the received analog input video signal in response to a clock signal which is supplied from the drive control circuit

2

, converts it to pixel data D of, for example, 4 bits corresponding to each pixel, and supplies it to the memory

4

.

When the sync detecting circuit

3

detects the vertical sync signal from the input video signal, it supplies a vertical sync detection signal V to each of the drive control circuit

2

and jitter detecting circuit

5

. When the sync detecting circuit

3

detects the horizontal sync signal from the input video signal, it supplies a horizontal sync detection signal H to the drive control circuit

2

.

The jitter detecting circuit

5

measures a period of the vertical sync detection signal V, thereby detecting whether a jitter due to a period fluctuation has occurred in the vertical sync signal in the input video signal or not. When no jitter occurs, the jitter detecting circuit

5

supplies a jitter detection signal JD at the logic level “0” to the drive control circuit

2

. When the jitter occurs, the jitter detecting circuit

5

supplies a jitter detection signal JD at the logic level “1” to the drive control circuit

2

.

The drive control circuit

2

generates a clock signal to the A/D converter

1

and generates write and read signals to the memory

4

synchronously with the vertical sync detection signal V and horizontal sync detection signal H.

The memory

4

sequentially writes the pixel data D in response to the write signal supplied from the drive control circuit

2

. By the writing operation, for example, when the writing of the pixel data D

11-nm

of one picture plane (n rows, m columns) in the PDP

10

is finished, the pixel data D

11-nm

of one picture plane is read out from the memory

4

every bit digit in accordance with a read signal supplied from the drive control signal

2

.

That is, the pixel data D

11-nm

is divided every bit digit into

DB

1

11-nm

: the first bit of the pixel data D

11-nm

DB

2

11-nm

: the second bit of the pixel data D

11-nm

DB

3

11-nm

: the third bit of the pixel data D

11-nm

DB

4

11-nm

: the fourth bit of the pixel data D

11-nm

and the divided pixel data DB

1

11-nm

to DB

4

11-nm

are sequentially read out every row and supplied to the address driver

6

.

When the logic level of the jitter detection signal JD is equal to “0”, namely, when no jitter occurs in the vertical sync signal in the input video signal, the drive control circuit

2

supplies various timing signals to drive the PDP

10

in accordance with a light emission driving format shown in

FIG. 2A

to the address driver

6

, first sustain driver

7

, and second sustain driver

8

, respectively. When the logic level of the jitter detection signal JD is equal to “1”, namely, if the jitter due to the period fluctuation occurred in the vertical sync signal in the input video signal, the drive control circuit

2

supplies various timing signals to drive the PDP

10

in accordance with a light emission driving format shown in

FIG. 2B

to the address driver

6

, first sustain driver

7

, and second sustain driver

8

, respectively.

In the light emission driving formats shown in

FIGS. 2A and 2B

, a display period of one field is divided into four sub-fields comprising sub-fields SF

1

to SF

4

and the light emission driving is performed. In this instance, in each sub-field, an all-resetting step Rc, a pixel data writing step Wc, a light emission sustaining step Ic, and an erasing step E are executed, respectively.

FIG. 3

is a diagram showing applying timings (in one sub-field) of various driving pulses which are applied from the address driver

6

, first sustain driver

7

, and second sustain driver

8

to the column electrodes D and the row electrodes X and Y of the PDP

10

in response to the various timing signals supplied from the drive control circuit

2

, respectively.

First, in the all-resetting step Rc, the first sustain driver

7

applies reset pulses RP

x

of a positive polarity to the row electrodes X

1

to X

n

. At the same time, the second sustain driver

8

applies reset pulses RP

Y

of a negative polarity to the row electrodes Y

1

to Y

n

. By simultaneously applying the reset pulses RP

X

and RP

Y

, all of the discharge cells in the PDP

10

are reset discharged and predetermined wall charges are uniformly formed in each discharge cell. All of the discharge cells in the PDP

10

, thus, are once initially set to the “light emitting cell”.

In the pixel data writing step Wc, the address driver

6

allocates DB

1

11-nm

, DB

2

11-nm

DB

3

11-nm

, and DB

4

11-nm

supplied from the memory

4

as mentioned above to the respective sub-fields, forms pixel data pulse groups DP

1

to DP

n

having a voltage corresponding to the logic level of each bit every row, and sequentially applies them to the column electrodes D

1-m

. For example, in the pixel data writing step Wc of the sub-field SF

1

, first, the pixel data pulse group DP

1

comprising pixel data pulses corresponding to the first row of DB

1

11-nm

, namely, m pixel data pulses corresponding to each logic level of DB

1

11-nm

are formed and applied to the column electrodes D

1-m

. Subsequently, the pixel data pulse group DP

2

comprising m pixel data pulses corresponding to each logic level of DB

1

21-2m

corresponding to the second row of DB

1

11-nm

are formed and simultaneously applied to the column electrodes D

1-m

. In a manner similar to the above, the pixel data pulse groups DP

3

to DP

n

of each row are sequentially applied to the column electrodes D

1-m

. In the pixel data writing step Wc of the sub-field SF

2

, the address driver

6

first forms the pixel data pulse group DP

1

comprising the pixel data pulses corresponding to the first row of DB

2

11-nm

, namely, m pixel data pulses corresponding to each logic level of DB

2

11-nm

and applies them to the column electrodes D

1-m

. Subsequently, the pixel data pulse group DP

2

comprising m pixel data pulses corresponding to each logic level of DB

2

21-2m

corresponding to the second row of DB

2

11-nm

are formed and simultaneously applied to the column electrodes D

1-m

. In a manner similar to the above, the pixel data pulse groups DP

3

to DP

n

of each row are sequentially applied to the column electrodes D

1-m

. It is assumed that when the logic level of DB is equal to “1”, the address driver

6

forms the pixel data pulses of a high voltage and, when the logic level is equal to “0”, it forms the pixel data pulses of a low voltage (0 volt).

The second sustain driver

8

generates scan pulses SP of a negative polarity as shown in

FIG. 3

at the same timing as each applying timing of the pixel data pulse group DP as mentioned above and sequentially applies them to the row electrodes Y

1

to Y

n

. In this instance, a discharge (selective erasing discharge) occurs only in the discharge cell existing in a cross portion of the “row” to which the scan pulses SP have been applied and the “column” to which the pixel data pulses of the high voltage have been applied. The wall charges remaining in the discharge cell are selectively erased. By the selective erasing discharge, the discharge cells initialized to the state of the “light emitting cell” by the all-resetting step Rc are shifted to the “non-light emitting cell”. No discharge is caused in the discharge cells formed in the “column” to which the pixel data pulses of the low voltage have been applied. The state initialized by the all-resetting step Rc, namely, the state of the “light emitting cell” is maintained. Further, the second sustain driver

8

applies priming pulses PP of a positive polarity to the row electrodes Y

1

to Y

n

as shown in

FIG. 3

just before the scan pulses SP are applied to each row electrode Y. A priming discharge occurs every row in response to the supply of the priming pulses PP. By the priming discharge, the charged particles reduced with the elapse of the time although they were obtained by the all-resetting operation are formed again in the discharge space of the PDP

10

. Since the scan pulses SP are, therefore, applied just after the charged particles were formed again, the selective erasing discharge is certainly caused and an erroneous writing operation of the pixel data is prevented.

In a light emission sustaining step Ic, subsequently, the first sustain driver

7

and second sustain driver

8

alternately apply sustain pulses IP

X

and IP

Y

of a positive polarity to the row electrodes X

1

to X

n

and Y

1

to Y

n

. In the light emission sustaining step Ic, the number of times (period) of applying the sustain pulses IP

X

and IP

Y

has been preset every sub-field SF.

For example, as shown in

FIGS. 2A and 2B

, now assuming that the number of light emission times in the sub-field SF

1

is equal to “4”, the sustain pulses IP

X

and IP

Y

are applied in the light emission sustaining step Ic of each sub-field only the following number of times (period).

SF

1

: 4

SF

2

: 8

SF

3

: 16

SF

4

: 32

By applying the sustain pulses IP, the discharge cells in which the wall charges remain in the pixel data writing step Wc, namely, the “light emitting cells” sustain discharge and perform the light emission each time the sustain pulses IP

X

and IP

Y

are applied and maintain the light emitting state only the number of times (period) allocated to each sub-field.

In an erasing step E which is executed at the end of one sub-field, the second sustain driver

8

applies erasing pulses EP of a negative polarity as shown in

FIG. 3

to the row electrodes X

1

to X

n

, thereby erasure discharging all of the discharge cells in a lump and erasing the wall charges remaining in each discharge cell.

The operation in one sub-field as mentioned above is executed in each of the sub-fields SF

1

to SF

4

in

FIGS. 2A and 2B

, thereby performing the light emission driving in which halftone luminance of 15 stages as shown in

FIG. 4

can be expressed. For example, when a value of the pixel data D corresponding to the input video signal is equal to “0101”, the light emission by the sustain discharge occurs only in the light emission sustaining step Ic in each of the sub-fields SF

1

and SF

3

among the sub-fields SF

1

to SF

4

. The luminance display corresponding to “20” as a total number of “4” and “16” as the numbers of light emission times of both of them is performed.

In the plasma display apparatus shown in

FIG. 1

, when no jitter occurs in the vertical sync signal in the input video signal, the light emission driving format shown in

FIG. 2A

is used. When the jitter exists, the light emission driving format shown in

FIG. 2B

is used. That is, when the jitter occurs in the vertical sync signal in the input video signal, for example, as shown in

FIG. 3

, by shortening an applying period Ts and/or a pulse width Wi of the scan pulses, an execution time Tb in each pixel data writing step Wc is set to be shorter than a time Ta in the case where no jitter occurs as shown in FIG.

2

A. When the jitter occurs in the vertical sync signal, consequently, the time that is required in the whole pixel data writing step Wc is reduced, so that the driving time that is required for display of one field is also reduced. The applying period and pulse width of the pixel data pulse DP are also controlled in accordance with the jitter in the vertical sync signal in a manner similar to the case of the scan pulses SP.

Even if the display period of one field becomes short since the jitter occurs in the input video signal, therefore, the driving time in one field is adjusted in the shortening direction from

FIG. 2A

to

FIG. 2B

in response to it. All of the sub-fields SF

1

to SF

4

, thus, can be executed within the 1-field period.

Although the execution time of the pixel data writing step Wc of each sub-field is adjusted in accordance with the jitter in the embodiment, the execution time of the light emission sustaining step Ic can be also adjusted in place of the pixel data writing step Wc.

FIGS. 5A and 5B

are diagrams showing another example of a light emission driving format made in consideration of the above point.

As shown in

FIG. 5B

, when the jitter occurs in the vertical sync signal in the input video signal, the number of times of light emission which is executed in the light emission sustaining step Ic of each sub-field, namely, the number of applying times of the sustain pulses IP

X

and IP

Y

is set to be smaller than that in the case where no jitter occurs as shown in

FIG. 5A

, thereby shortening the driving period of one field.

Although the number of times of light emission which is executed in each light emission sustaining step Ic is adjusted in the embodiment shown in

FIGS. 5A and 5B

, an applying period Ti and/or the pulse width Wi of the sustain pulse can be also adjusted in place of the number of light emission times. That is, when the jitter occurs in the vertical sync signal, as shown in

FIG. 3

, the applying period Ti and/or the pulse width Wi of the sustain pulse is shortened than that in the case where no jitter occurs, thereby adjusting the execution time of each light emission sustaining step Ic.

To reduce the driving period of one field, the sub-field to perform the light emission for the low luminance component can be omitted.

FIGS. 6A and 6B

are diagrams showing another example of a light emission driving format made in consideration of the above point.

As shown in

FIG. 6B

, when the jitter occurs in the vertical sync signal in the input video signal, by omitting the light emission driving operation in the sub-field SF

1

to perform the display for the low luminance component, the driving period of one field is set to a period shorter than that in the case where no jitter occurs as shown in FIG.

6

A.

Although the constructions such that any of the execution time of the writing step, the execution time of the light emission sustaining step, and the number of sub-fields to be executed within the display period of one field is adjusted have been shown in the embodiments, those constructions can be also properly combined and used. In this case, the driving time that is required for display of one field is further reduced.

Although the operation has been described in the embodiment with respect to the example in the case where one field is divided into four sub-fields and the halftone luminance display is performed, the number of sub-fields to be divided is not limited to 4.

Further, although the operation in the case where the invention is applied to the light emission driving format such that each of the all-resetting step Rc, pixel data writing step Wc, light emission sustaining step Ic, and erasing step E is executed for every sub-field has been described in the embodiment, the invention is not limited to it.

For example, as shown in

FIG. 7

, the invention can be also applied to a light emission driving format such that the all-resetting step Rc is executed only in the head sub-field SF

1

of one field and the erasing step E is executed only in the last sub-field SF

14

.

In the light emission driving format shown in

FIG. 7

, the display period of one field is divided into 14 sub-fields SF

1

to SF

14

and the PDP is driven. In each sub-field, the pixel data writing step Wc of writing the pixel data to each discharge cell of the PDP and setting the “light emitting cell” and the “non-light emitting cell” and the light emission sustaining step Ic of maintaining the light emitting state by allowing only the “light emitting cells” to perform the light emission only the number of times (period) shown in

FIG. 7

are executed. In this instance, now assuming that the number of times of light emission which is executed in the light emission sustaining step Ic of the sub-field SF

1

is set to “4”, the number of times of light emission which is executed in the light emission sustaining step Ic of each sub-field is set as follows.

SF

1

: 4

SF

2

: 12

SF

3

: 20

SF

4

: 32

SF

5

: 40

SF

6

: 52

SF

7

: 64

SF

8

: 76

SF

9

: 88

SF

10

: 100

SF

11

: 112

SF

12

: 128

SF

13

: 140

SF

14

: 156

The all-resetting step Rc of initializing an amount of wall charges in all of the discharge cells of the PDP is executed only in the head sub-field SF

1

and the erasing step E of erasing the wall charges in all of the discharge cells in a lump is executed only in the last sub-field SF

14

.

FIG. 8

is a diagram showing a construction of a plasma display apparatus for gradation driving a plasma display panel on the basis of the light emission driving format shown in FIG.

7

.

As shown in

FIG. 8

, the plasma display apparatus is constructed by: the PDP

10

serving as a plasma display panel; and a driving unit comprising the A/D converter

1

, the drive control circuit

2

, the sync detecting circuit

3

, a data converting circuit

30

, the memory

4

, the jitter detecting circuit

5

, the address driver

6

, the first sustain driver

7

, and the second sustain driver

8

.

The PDP

10

has: m column electrodes D

1

to D

m

serving as address electrodes; and n row electrodes X

1

to X

n

and n row electrodes Y

1

to Y

n

arranged so as to cross the column electrodes, respectively. In this instance, the row electrodes corresponding to one row in the PDP

10

are formed by pairs of row electrodes X and row electrodes Y. The column electrodes D and the row electrodes X and Y are covered with a dielectric material layer against a discharge space and have a structure such that a discharge cell corresponding to one pixel is formed at a cross point of each row electrode pair and the column electrode.

The A/D converter

1

samples the received analog input video signal in response to the clock signal which is supplied from the drive control circuit

2

, converts it to the pixel data D of, for example, 8 bits corresponding to each pixel, and supplies it to the data converting circuit

30

.

The data converting circuit

30

converts the pixel data D of 8 bits to conversion pixel data HD of 14 bits for actually driving the PDP

10

and supplies it to the memory

4

.

FIG. 9

is a diagram showing an internal construction of the data converting circuit

30

.

In

FIG. 9

, a first data converting circuit

32

converts the 8-bit pixel data D of each pixel which is sequentially supplied from the A/D converter

1

to conversion pixel data HDP of 8 bits (0˜224) by performing a conversion of (14×16)/255 on the basis of converting characteristics as shown in FIG.

10

and supplies it to a multi-gradation processing circuit

33

. Specifically speaking, the pixel data D of 8 bits (0˜255) is converted in accordance with conversion tables shown in

FIGS. 11 and 12

based on the converting characteristics. The converting characteristics are set in accordance with the number of bits of the pixel data D, the number of bits to be compressed by a multi-gradation process of the multi-gradation processing circuit

33

, and the number of display gradations. As mentioned above, by providing the first data converting circuit

32

at the front stage of the multi-gradation process and performing the conversion in accordance with the number of display gradations and the number of compression bits due to the multi-gradation, the pixel data D is separated into a group of upper bits (corresponding to the multi-gradation pixel data) and a group of lower bits (data to be omitted: error data) at a bit boundary. The multi-gradation process by the multi-gradation processing circuit

33

is performed on the basis of this signal.

By the data conversion by the first data converting circuit

32

as mentioned above, the occurrence of luminance saturation in the multi-gradation processing circuit

33

and the occurrence of a flat portion of display characteristics (namely, the occurrence of a gradation distortion) which is caused when the display gradation does not exist at the bit boundary are prevented.

FIG. 13

is a diagram showing an internal construction of the multi-gradation processing circuit

33

.

As shown in

FIG. 13

, the multi-gradation processing circuit

33

is constructed by an error diffusion processing circuit

330

and a dither processing circuit

350

.

A data separating circuit

331

in the error diffusion processing circuit

330

separates the data of lower two bits in the 8-bit conversion pixel data HD

P

supplied from the first data converting circuit

32

as error data and separates the data of six upper bits as display data. An adder

332

adds the data of lower two bits in the conversion pixel data HDP as error data, a delay output from a delay circuit

334

, and a multiplication output of a coefficient multiplier

335

and supplies an obtained addition value to a delay circuit

336

. The delay circuit

336

delays the addition value supplied from the adder

332

by only a delay time D having the same time as the clock period of the pixel data and supplies a resultant delayed signal as a delay addition signal AD

1

to the coefficient multiplier

335

and a delay circuit

337

, respectively. The coefficient multiplier

335

multiplies the delay addition signal AD

1

by a predetermined coefficient value K

1

(for example, “{fraction (7/16)}”) and supplies an obtained multiplication result to the adder

332

. The delay circuit

337

further delays the delay addition signal AD

1

by only the time of (one horizontal scan period−the delay time D×4) and supplies a resultant signal as a delay addition signal AD

2

to a delay circuit

338

. The delay circuit

338

further delays the delay addition signal AD

2

by only the delay time D and supplies a resultant signal as a delay addition signal AD

3

to a coefficient multiplier

339

. The delay circuit

338

further delays the delay addition signal AD

2

by only the time of (the delay time D×2) and supplies an obtained signal as a delay addition signal AD

4

to a coefficient multiplier

340

. The delay circuit

338

further delays the delay addition signal AD

2

by only the time of (the delay time D×3) and supplies an obtained signal as a delay addition signal AD

5

to a coefficient multiplier

341

. The coefficient multiplier

339

multiplies the delay addition signal AD

3

by a predetermined coefficient value K

2

(for example, “{fraction (3/16)}”) and supplies an obtained multiplication result to an adder

342

. The coefficient multiplier

340

multiplies the delay addition signal AD

4

by a predetermined coefficient value K

3

(for example, “{fraction (5/16)}”) and supplies an obtained multiplication result to the adder

342

. The coefficient multiplier

341

multiplies the delay addition signal AD

5

by a predetermined coefficient value K

4

(for example, “{fraction (1/16)}”) and supplies an obtained multiplication result to the adder

342

. The adder

342

adds multiplication results supplied from the coefficient multipliers

339

,

340

, and

341

and supplies an obtained addition signal to the delay circuit

334

. The delay circuit

334

delays the addition signal by only a time of the delay time D and supplies the delayed signal to the adder

332

. When the data of lower two bits in the conversion pixel data HD

P

, a delay output from the delay circuit

334

, and a multiplication output of the coefficient multiplier

335

are added, if there is no carry, the adder

332

generates a carry-out signal Co at the logic level “0” and supplies it to an adder

333

. When there is a carry, the adder

332

generates the carry-out signal Co at the logic level “1” and supplies it to the adder

333

. The adder

333

adds the carry-out signal Co to the display data consisting of upper six bits in the conversion pixel data HD

P

and outputs an obtained addition data as error diffusion processing pixel data ED of 6 bits. That is, the number of bits of the error diffusion processing pixel data ED is smaller than the conversion pixel data HD

P

.

The operation of the error diffusion processing circuit

330

will now be described.

For example, in case of obtaining the error diffusion processing pixel data ED corresponding to a pixel G(j,k) of the PDP

10

as shown in

FIG. 14

, first, error data corresponding to a pixel G(j,k−1) existing on the left side of the pixel G(j,k), a pixel G(j−1,k−1) existing at a left oblique upper position, a top pixel G(j−1,k), and a pixel G(j−1,k+1) existing at a right oblique upper position, namely,

error data corresponding to the pixel G(j,k−1):

delay addition signal AD

1

error data corresponding to the pixel G(j−1,k+1):

delay addition signal AD

3

error data corresponding to the pixel G(j−1,k):

delay addition signal AD

4

error data corresponding to the pixel G(j−1,k−1):

delay addition signal AD

5

are weighted by the predetermined coefficient values K

1

to K

4

as mentioned above and resultant weighted data is added. Subsequently, the error data corresponding to the data of lower two bits of the conversion pixel data HD

P

, namely, the error data corresponding to the pixel G(j,k) is added to the addition result. The carry-out signal Co of one bit obtained in this instance is added to the display data corresponding to the data of upper 6 bits in the conversion pixel data HD

P

, namely, the display data corresponding to the pixel G(j,k) and resultant addition data is set to the error diffusion processing pixel data ED.

By the above construction, in the error diffusion processing circuit

330

, the data of upper 6 bits in the conversion pixel data HD

P

is regarded as display data, the data of remaining lower two bits is regarded as error data, and the data obtained by weighting and adding the error data in the peripheral pixels {G(j,k−1), G(j−1,k+1), G(j−1,k), G(j−1,k−1)} is reflected to the display data. Since the luminance of lower 2 bits in the original pixel {G(j,k)} is falsely expressed by the peripheral pixels by the above operation, the luminance gradation expression that is substantially equivalent to that of the pixel data of 8 bits can be realized by the display data of the bits of the number smaller than 8 bits, namely, by the display data of 6 bits.

If coefficient values of the error diffusion were uniformly added to each pixel, there is a case where noises generated by an error diffusion pattern are visually confirmed, so that the picture quality is deteriorated. To prevent such a phenomenon, therefore, the error diffusion coefficients K

1

to K

4

to be allocated to the respective four pixels can be also changed every field in a manner similar to the case of dither coefficients, which will be explained hereinlater.

A dither processing circuit

350

performs a dither process to the 6-bit error diffusion processing pixel data ED supplied from the error diffusion processing circuit

330

, thereby forming multi-gradation processing pixel data D

s

in which the number of bits is reduced to 4 bits while maintaining the luminance gradation level equivalent to that of the error diffusion processing pixel data ED. In the dither process, one intermediate display level is expressed by a plurality of neighboring pixels. For example, in case of performing the gradation display corresponding to 8 bits by using the pixel data of upper 6 bits in the 8-bit pixel data, four pixels which are neighboring at the right/left positions and the upper/lower positions are constructed as one set, four dither coefficients a to d comprising different coefficient values are allocated to the respective pixel data corresponding to the pixels of one set, and the resultant data is added. According to the dither process, combinations of four different intermediate display levels are generated with respect to four pixels. Even if the number of bits of the pixel data is equal to 6, therefore, the luminance gradation level which can be expressed can be increased four times, namely, the halftone display corresponding to 8 bits can be realized.

If the dither pattern of the dither coefficients a to d was uniformly added to each pixel, there is a case where noises generated due to the dither pattern is visually confirmed, so that the picture quality is deteriorated.

In the dither processing circuit

350

, accordingly, the dither coefficients a to d to be allocated to the four pixels are changed every field.

FIG. 15

is a diagram showing an internal construction of the dither processing circuit

350

.

In

FIG. 15

, a dither coefficient generating circuit

352

generates four dither coefficients a, b, c, and d for every four adjacent pixels and sequentially supplies them to an adder

351

. For example, the four dither coefficients a, b, c, and d are generated for four pixels comprising the pixels G(j,k) and G(j,k+1) corresponding to the jth row and the pixels G(j+1,k) and G(j+1,k+1) corresponding to the (j+1) throw as shown in FIG.

16

. In this instance, the dither coefficient generating circuit

352

changes the dither coefficients a to d to be allocated to the four pixels every field as shown in FIG.

16

.

That is, the dither coefficients a to d are cyclically and repetitively generated by allocating as follows.

In the first field,

pixel G(j,k): dither coefficient a

pixel G(j,k+1):dither coefficient b

pixel G(j+1,k):dither coefficient c

pixel G(j+1,k+1): dither coefficient d

In the second field,

pixel G(j,k): dither coefficient b

pixel G(j,k+1):dither coefficient a

pixel G(j+1,k):dither coefficient d

pixel G(j+1,k+1): dither coefficient c

In the third field,

pixel G(j,k): dither coefficient d

pixel G(j,k+1):dither coefficient c

pixel G(j+1k):dither coefficient b

pixel G(j+1,k+1): dither coefficient a

In the fourth field,

pixel G(j,k): dither coefficient c

pixel G(j,k+1):dither coefficient d

pixel G(j+1,k):dither coefficient a

pixel G(j+1,k+1): dither coefficient b

The resultant data is supplied to the adder

351

. The dither coefficient generating circuit

352

repetitively executes the operations of the first to the fourth fields as mentioned above. That is, when the dither coefficient generating operation in the fourth field is finished, the operation is again returned to the operation in the first field and the foregoing operations are repeated.

The adder

351

adds the dither coefficients a to d allocated to each field as mentioned above to each of the error diffusion processing pixel data ED corresponding to each of the pixels G(j,k), G(j,k+1), G(j+1,k), and G(j+1,k+1) supplied from the error diffusion processing circuit

330

, respectively, and supplies the dither addition pixel data obtained in this instance to an upper bit extracting circuit

353

.

For example, in the first field shown in

FIG. 16

, each of the following data

error diffusion processing pixel data ED corresponding to the pixel G(j,k)+dither coefficient a

error diffusion processing pixel data ED corresponding to the pixel G(j,k+1)+dither coefficient b

error diffusion processing pixel data ED corresponding to the pixel G(j+1,k)+dither coefficient c

error diffusion processing pixel data ED corresponding to the pixel G(j+1,k+1)+dither coefficient d

is sequentially supplied as dither addition pixel data to the upper bit extracting circuit

353

.

The upper bit extracting circuit

353

extracts the data corresponding to upper 4 bits of the dither addition pixel data and supplies it as multi-gradation pixel data D

s

to a second data converting circuit

34

shown in FIG.

9

.

The second data converting circuit

34

converts the multi-gradation pixel data D

s

of 4 bits to the conversion pixel data HD of 14 bits in accordance with a conversion table as shown in FIG.

17

.

As mentioned above, in the data converting circuit

30

, first, by performing the error diffusion and the multi-gradation process such as a dither process to the 8-bit pixel data D, thereby obtaining the multi-gradation pixel data D

s

in which the number of bits is reduced to 4 bits while maintaining the number of gradations of the luminance on the sense of sight. Subsequently, the multi-gradation pixel data D

s

is converted to the 14-bit conversion pixel data HD for actually driving the PDP

10

in accordance with the conversion table as shown in FIG.

17

.

The 14-bit conversion pixel data HD converted and outputted by the data converting circuit

30

is sequentially written in the memory

4

in response to the write signal supplied from the drive control circuit

2

. When the writing of the conversion pixel data HD

11-nm

as much as one picture plane (n rows, m columns) is finished by the writing operation, the conversion pixel data HD

11-nm

of one picture plane is divided every bit digit, namely,

DB

1

11-nm

: the 1st bit of the conversion pixel

data HD

11-nm

DB

2

11-nm

: the 2nd bit of the conversion pixel

data HD

11-nm

DB

3

11-nm

: the 3rd bit of the conversion pixel data HD

11-nm

DB

4

11-nm

: the 4th bit of the conversion pixel data HD

11-nm

DB

5

11-nm

: the 5th bit of the conversion pixel data HD

11-nm

DB

6

11-nm

: the 6th bit of the conversion pixel data HD

11-nm

DB

7

11-nm

: the 7th bit of the conversion pixel data HD

11-nm

DB

8

11-nm

: the 8th bit of the conversion pixel data HD

11-nm

DB

9

11-nm

: the 9th bit of the conversion pixel data HD

11-nm

DB

10

11-nm

: the 10th bit of the conversion pixel data HD

11-nm

DB

11

11-nm

: the 11th bit of the conversion pixel data HD

11-nm

DB

12

11-nm

: the 12th bit of the conversion pixel data HD

11-nm

DB

13

11-nm

: the 13th bit of the conversion pixel data HD

11-nm

DB

14

11-nm

: the 14th bit of the conversion pixel data HD

11-nm

each of DB

1

11-nm

, DB

2

11-nm

, . . . , DB

14

11-nm

is sequentially read out every row from the memory

4

in response to the read signal supplied from the drive control circuit

2

and is supplied to the address driver

6

.

When the logic level of the jitter detection signal JD supplied from the jitter detecting circuit

5

is equal to “0”, namely, when no jitter occurs in the vertical sync signal in the input video signal, the drive control circuit

2

supplies various timing signals for driving the PDP

10

in accordance with a light emission driving format shown in

FIG. 18A

to the address driver

6

, first sustain driver

7

, and second sustain driver

8

, respectively. When the logic level of the jitter detection signal JD is equal to “1”, namely, when the jitter occurs in the vertical sync signal in the input video signal, the drive control circuit

2

supplies various timing signals for driving the PDP

10

in accordance with a light emission driving format shown in

FIG. 18B

to the address driver

6

, first sustain driver

7

, and second sustain driver

8

, respectively. The light emission driving format shown in

FIG. 18A

is the same as that shown in

FIG. 7

mentioned above.

FIG. 19

is a diagram showing applying timings (in one field) of various driving pulses which are applied to the column electrodes D and row electrodes X and Y of the PDP

10

from the address driver

6

, first sustain driver

7

, and second sustain driver

8

in response to the various timing signals supplied from the drive control circuit

2

, respectively.

In

FIG. 19

, first, in the all-resetting step Rc which is executed only in the sub-field SF

1

, the reset pulses RP

X

of a negative polarity and the reset pulses RP

Y

of a positive polarity as shown in the diagram are simultaneously applied to the row electrodes X

1

to X

n

and Y

1

to Y

n

. The first sustain driver

7

and second sustain driver

8

apply the reset pulses RP

X

and RP

Y

, all of the discharge cells in the PDP

10

are reset discharged and predetermined wall charges are uniformly formed in each discharge cell. All of the discharge cells in the PDP

10

, consequently, are once initially set to the “light emitting cells”.

In the pixel data writing step Wc in each sub-field, the address driver

6

generates the pixel data pulse groups DP

1

11-nm

to DP

14

11-nm

having the voltages corresponding to the logic levels from each of DB

1

11-nm

to DB

14

11-nm

supplied from the memory as mentioned above. The address driver

6

allocates each of the pixel data pulse groups DP

1

11-nm

to DP

14

11-nm

to the sub-fields SF

1

to SF

14

, respectively, and sequentially applies them one row by one to the column electrodes D

1-m

every sub-field. For example, in the pixel data writing step Wc of the sub-field SF

1

, first, the data corresponding to the first row, namely, DB

1

11-nm

are extracted from DB

1

11-nm

and the pixel data pulse group DP

1

1

comprising the m pixel data pulses corresponding to the logic level of each of DB

1

11-nm

are formed and applied to the column electrodes D

1-m

. Subsequently, DB

1

21-2m

corresponding to the second row of DB

1

11-nm

are extracted and the pixel data pulse group DP

1

2

comprising the m pixel data pulses corresponding to the logic level of each of DB

1

21-m2

are formed and simultaneously applied to the column electrodes D

1-m

. In a manner similar to the above, in the pixel data writing step Wc of the sub-field SF

1

, the pixel data pulse groups DP

1

3

to DP

1

n

of every row are sequentially applied to the column electrodes D

1-m

. It is assumed that when the logic level of DB

1

is equal to, for example, “1”, the address driver

6

forms pixel data pulses of a high voltage and, when the logic level of DB

1

is equal to “0”, the address driver

6

forms pixel data pulses of a low voltage (0 volt). In the pixel data writing step Wc of the sub-field SF

2

, first, the data corresponding to the first row, namely, DB

2

11-1m

are extracted from DB

2

11-nm

and the pixel data pulse group DP

2

1

comprising the m pixel data pulses corresponding to the logic level of each of DB

2

11-nm

are formed and applied to the column electrodes D

1-m

. Subsequently, DB

2

21-2m

corresponding to the second row of DB

2

11-nm

are extracted and the pixel data pulse group DP

2

2

comprising the m pixel data pulses corresponding to the logic level of each of DB

2

21-2m

are formed and simultaneously applied to the column electrodes D

1-m

. In a manner similar to the above, in the pixel data writing step Wc of the sub-field SF

2

, the pixel data pulse groups DP

2

3

to DP

2

n

of every row are sequentially applied to the column electrodes D

1-m

.

Even in the pixel data writing step Wc of each of the sub-fields SF

3

to SF

14

, the address driver

6

forms pixel data pulse groups DP

3

1-n

to DP

14

1-n

from each of DB

3

11-nm

to DB

14

11-nm

and sequentially applies them every row to the column electrodes D

1-m

in a manner similar to that of the foregoing method.

The second sustain driver

8

generates scan pulses SP of a negative polarity as shown in

FIG. 19

at the same timing as each applying timing of the pixel data pulse group DP as mentioned above and sequentially applies them to the row electrodes Y

1

to Y

n

. In this instance, a discharge (selective erasing discharge) occurs only in the discharge cell existing in a cross portion of the “row” to which the scan pulses SP have been applied and the “column” to which the pixel data pulses of the high voltage have been applied. The wall charges remaining in the discharge cell are selectively erased. By the selective erasing discharge, the discharge cells initialized to the state of the “light emitting cell” by the all-resetting step Rc are shifted to the “non-light emitting cell”. No discharge is caused in the discharge cells formed in the “column” to which the pixel data pulses of the low voltage have been applied. The state initialized by the all-resetting step Rc, namely, the state of the “light emitting cell” is maintained.

In the light emission sustaining step Ic in each sub-field, subsequently, the first sustain driver

7

and second sustain driver

8

alternately apply sustain pulses IP

X

and IP

Y

of a positive polarity to the row electrodes X

1

to X

n

and Y

1

to Y

n

. In the light emission sustaining step Ic in each sub-field, the number of times (period) of applying the sustain pulses IP

X

and IP

Y

has been preset every sub-field SF. That is, as shown in

FIGS. 18A and 18B

, now assuming that the number of times of light emission which is executed in the sub-field SF

1

is set to “4”, the sustain pulses IP

X

and IP

Y

are applied in the light emission sustaining step Ic in each sub-field only the following number of times of light emission (period).

SF

1

: 4

SF

2

: 12

SF

3

: 20

SF

4

: 32

SF

5

: 40

SF

6

: 52

SF

7

: 64

SF

8

: 76

SF

9

: 88

SF

10

: 100

SF

11

: 112

SF

12

: 128

SF

13

: 140

SF

14

: 156

By applying the sustain pulses IP, the discharge cells whose wall charges remain in the pixel data writing step Wc, namely, the “light emitting cells” sustain discharge each time the sustain pulses IP

X

and IP

Y

are applied and maintain the discharge light emitting state only the number of times (period) allocated every sub-field. According to the light emission sustaining step Ic of the sub-field SF

1

, therefore, the light emission display for the low luminance component of the input video signal is performed and, according to the light emission sustaining step Ic of the sub-field SF

14

, the light emission display for the high luminance component is performed.

As shown in

FIG. 19

, the erasing step E which is executed only in the last sub-field SF

14

, the address driver

6

generates erasing pulses AP and applies them to each of the column electrodes D

1-m

. The second sustain driver

8

generates the erasing pulses EP simultaneously with the applying timings of the erasing pulses AP and applies them to each of the row electrodes Y

1

to Y

n

. By simultaneously applying the erasing pulses AP and EP, the erasing discharge is caused in all of the discharge cells in the PDP

10

and the wall charges remaining in all of the discharge cells are extinguished. That is, all of the discharge cells in the PDP

10

become the “non-light emitting cells” by the erasing discharge.

By executing the operation of one field as mentioned above, the light emission driving which can express the halftone luminance of 15 stages according to each of the conversion pixel data HD comprising total 15 patterns as shown in

FIG. 17

is performed.

FIG. 20

is a diagram showing the whole pattern of the light emission driving within the 1-field display period which is executed in accordance with each of the conversion pixel data HD.

A black circle shown in

FIG. 20

denotes that the selective erasing discharge is executed in the pixel data writing step Wc in the sub-field. That is, the wall charges formed in all of the discharge cells of the PDP

10

by the all-resetting step Rc in the head sub-field SF

1

continuously remain for a period of time until the selective erasing discharge is executed. The sustain discharge accompanied with the light emission is caused (shown by a white circle) in the light emission sustaining step Ic in each of the sub-fields existing during this period of time. As mentioned above, each discharge cell becomes the “light emitting cell” for a period of time until the selective erasing discharge is performed in one field and repeats the light emission only the number of times corresponding to each sub-field in the light emission sustaining step Ic in each sub-field existing during this interval.

According to the light emission driving pattern as shown in

FIG. 20

, therefore, the gradation driving of 15 stages in which the light emission luminance ratios are set to

{0, 4, 16, 36, 68, 108, 160, 224, 300, 388, 488, 600, 728, 868, 1024}

are executed.

The pixel data D which is supplied from the A/D converter

1

, however, expresses the halftones of 8 bits, namely, 256 stages. To realize the halftone luminance display near 256 stages, therefore, even in the gradation driving of 15 stages, the error diffusion and the multi-gradation process such as a dither are executed by the multi-gradation processing circuit

33

.

In the plasma display apparatus shown in

FIG. 8

, as mentioned above, when no jitter occurs in the vertical sync signal in the input video signal, the light emission driving format shown in

FIG. 18A

is used, and when the jitter exists, the light emission driving format shown in

FIG. 18B

is used.

That is, when the jitter occurs in the vertical sync signal in the input video signal, by shortening the applying period Ts and/or the pulse width Wi of the scan pulses SP as shown in

FIG. 19

, the execution time Tb that is required for the pixel data writing step Wc of each sub-field is adjusted to the time shorter than the execution time Ta in the case where no jitter occurs, thereby shortening the driving time that is required for display of one field. The applying period and the pulse width of the pixel data pulses DP are also controlled in a manner similar to the case of the scan pulses SP in accordance with the jitter of the vertical sync signal.

Even if the jitter exists in the vertical sync signal in the input video signal and, accordingly, the display period of one field becomes short, therefore, the driving time is adjusted in the reducing direction from

FIG. 18A

to

FIG. 18B

in response to it. All of the driving operations of the sub-fields SF

1

to SF

14

, thus, can be executed within the 1-field display period.

Although the execution time of the pixel data writing step Wc of each sub-field is adjusted in accordance with the jitter in the embodiments, the execution time of the light emission sustaining step Ic can be also adjusted in place of the pixel data writing step Wc.

FIGS. 21A and 21B

are diagrams showing another example of a light emission driving format made in consideration of the above point.

As shown in

FIG. 21B

, when the jitter occurs in the vertical sync signal in the input video signal, the number of times of light emission which is executed in the light emission sustaining step Ic of each sub-field, namely, the number of applying times of the sustain pulses IP

X

and IP

Y

is set to the value smaller than that in the case where no jitter occurs as shown in

FIG. 21A

, thereby shortening the driving period of one field.

Although the number of times of light emission which is executed in each light emission sustaining step Ic has been adjusted in the embodiment shown in

FIGS. 21A and 21B

, the applying period Ti and/or the pulse width Wi of the sustain pulses can be adjusted in place of the number of light emission times. That is, when the jitter occurs in the vertical sync signal, the applying period Ti and/or the pulse width Wi of the sustain pulses is set to a value shorter than that in the case where no jitter occurs as shown in

FIG. 19

, thereby adjusting the execution time of each light emission sustaining step Ic.

To shorten the driving period of one field, the driving operation by the sub-field for performing the light emission for the low luminance component can be omitted.

FIGS. 22A and 22B

are diagrams showing another example of light emission driving format made in consideration of the above point.

As shown in

FIG. 22B

, when the jitter occurs in the vertical sync signal in the input video signal, by omitting the driving operation by each of the sub-fields SF

1

and SF

2

to perform the display for the low luminance component, the driving period of one field is set to a value shorter than that in the case where no jitter occurs as shown in FIG.

22

A.

Although the constructions such that any of the execution time of the writing step, the execution time of the light emission sustaining step, and the number of sub-fields to be executed within the display period of one field is adjusted have been shown in the embodiments, those constructions can be also properly combined and used. In this case, the driving time that is required for display of one field is further reduced.

Although the selective erasing discharge is caused in the pixel data writing step Wc of any of the sub-fields SF

1

to SF

4

in the driving shown in

FIG. 20

, if an amount of charged particles remaining in the discharge cell is small, there is a case where even if the scan pulses SP and the pixel data pulses of the high voltage are simultaneously applied, the selective erasing discharge is not normally caused.

The selective erasing discharge can be also certainly caused by using a light emission driving pattern as shown in

FIG. 23

in place of the light emission driving pattern shown in FIG.

20

.

In the light emission driving shown in

FIG. 23

, the selective erasing discharge is continuously executed (shown by black circles) in the pixel data writing step Wc of each of at least two continuous sub-fields. According to this operation, even if the wall charges in the discharge cell cannot be normally extinguished by the selective erasing discharge of the first time, the wall charges are normally extinguished by the selective erasing discharge of the second time.

As shown by Δ in

FIG. 23

, in any of the sub-fields after the end of the selective erasing discharge of two times, by again executing the selective erasing discharge of the third and fourth times, the wall charges are more certainly extinguished.

As described above, according to the invention, at least one of the execution time of the writing step, the execution time of the light emission sustaining step, and the number of sub-fields to be executed within the display period of one field in each sub-field is adjusted in accordance with the jitter of the vertical sync signal in the input video signal.

Even if the display period of one field becomes short because the video signal in which the jitter occurred in the vertical sync signal is inputted, the driving time is also reduced in response to it, so that all of the sub-fields can be executed within the 1-field display period. The good image display having desired gradation luminance can be performed.

Number	Name	Date	Kind
4129748	Saylor	Dec 1978	A
5003228	Hada et al.	Mar 1991	A
5926174	Shibamiya et al.	Jul 1999	A
6097444	Nakano	Aug 2000	A

Method for driving a plasma display panel

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (1)

US Referenced Citations (4)