Patent Application
20240363084
The present disclosure relates to the field of display technology, and in particular to a method for driving a display panel, a display drive circuit and a display device.
Displays such as a liquid crystal display (LCD) and an organic light-emitting diode (OLED) generally include a plurality of pixels. Each pixel may include: a red sub-pixel, a green sub-pixel and a blue sub-pixel. By controlling display data corresponding to each sub-pixel, display brightness of each sub-pixel is controlled, so as to display a color image by mixing to-be-required and displayed colors.
Embodiments of the present disclosure provide a method for driving a display panel, where the display panel works in a plurality of continuous display frames, and each display frame includes a data refresh phase and a blanking time phase; and the method includes:
In some embodiments, the compensation voltage is loaded throughout the blanking time phase of the at least one display frame.
In some embodiments, the display panel adopts a column inversion method or a frame inversion method; the compensation voltage includes a first sub-compensation voltage;
In some embodiments, the display frame, in which the compensation voltage is loaded to each data line in the blanking time phase, has a first display frame and a second display frame;
In some embodiments, the display frame, in which the compensation voltage is loaded to each data line in the blanking time phase, is defined as a set display frame; in two adjacent set display frames, for a same data line, the first sub-compensation voltage loaded to the data line in a previous set display frame and the common electrode voltage have a first difference therebetween, and the first sub-compensation voltage loaded to the data line in a next set display frame and the common electrode voltage have a second difference therebetween; and
In some embodiments, the compensation voltage further includes a transition compensation voltage that appears before the first sub-compensation voltage;
In some embodiments, the display panel adopts a column inversion method or a frame inversion method; the compensation voltage includes a second sub-compensation voltage;
In some embodiments, the display frame, in which the compensation voltage is loaded to each data line in the blanking time phase, is defined as a set display frame;
In some embodiments, at least one non-set display frame exists between two adjacent set display frames.
In some embodiments, a quantity of the non-set display frames between every two adjacent set display frames is the same.
In some embodiments, a gray scale corresponding to the compensation voltage loaded on each data line is the same.
In some embodiments, for each data line, the gray scale corresponding to the compensation voltage loaded on the data line is the same as a gray scale corresponding to one data voltage of the sub-pixel connected with the data line.
In some embodiments, the gray scale corresponding to the compensation voltage is determined by using the following formula:
In some embodiments, the gray scale corresponding to the compensation voltage is determined by using the following formula:
In some embodiments, the loading the compensation voltage to each data line, includes: in the blanking time phase of a set display frame, selecting a display frame from the plurality of display frames, and for each data line, and loading a voltage of a gray scale, corresponding to a data voltage input into a row of sub-pixels of the display panel in the selected display frame, to the data line.
In some embodiments, the loading the compensation voltage to each data line, includes:
In some embodiments, the loading the compensation voltage to each data line, includes:
In some embodiments, the display frame selected from the plurality of display frames is one of a previous display frame adjacent to the set display frame and the set display frame.
Embodiments of the present disclosure provides a display drive circuit, where a display panel works in a plurality of continuous display frames, and each display frame includes a data refresh phase and a blanking time phase; and
Embodiments of the present disclosure provides a display device, including a display panel and a timing controller; where,
In order to make the purposes, technical solutions and advantages of embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative effort fall within the protection scope of the present disclosure.
Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have usual meanings understood by those skilled in the art to which the present disclosure belongs. “First”, “second” and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. “Comprise” or “include” and similar words mean that elements or items appearing before the word include elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as “connect” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that a size and shape of each figure in the drawings do not reflect a true scale, but are only intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
A current display frequency is generally 60 HZ, that is, a screen of a display is refreshed 60 times per second, so that the screen seen by human eyes is dynamic and smooth. However, in some application scenarios, in order to reduce power consumption of the display, it is necessary to reduce a frequency of the display, for example, reducing from 60 HZ to 30 HZ. In other scenarios, for example, when performing high-frequency games, it is necessary to increase a frequency of the display, for example, increasing from 60 HZ to 90 HZ or 120 HZ, so as to make the screen smoother. Therefore, in order to be suitable for different scenarios, the display needs to change the display frequency, that is, a dynamic frame rate display.
As shown in
As shown in
As shown in
When a display frequency of a display is changed from a high frequency to a low frequency, if the display displays a same image, brightness of the image displayed at the low frequency is higher than brightness of the image displayed at the high frequency. This is caused by a fact that a charging rate in a data refresh stage at the low frequency is higher than a charging rate in a data refresh stage at the high frequency. Although a transistor in a sub-pixel has a leakage phenomenon in the blanking time phase, in this case, the leakage phenomenon of the transistor accounts for a smaller proportion than a charging rate. In order to keep brightness stable when the display is switched under different frequencies, avoid abnormal display images caused by switching frequencies, improve display quality of the display, and improve view experience, embodiments of the present disclosure provide a method for driving a display panel, which can solve the problem of increased brightness of a display image when the display frequency of the display changes from the high frequency to the low frequency, maintain stable brightness, and improve display quality and view experience.
In the method for driving the display panel in the embodiments of the present disclosure, the display panel works in a plurality of continuous display frames, and each display frame may include a data refresh phase and a blanking time phase. In the data refresh phase of at least one display frame of the plurality of continuous display frames, a gate-on voltage is loaded to a gate line(s) in the display panel, and a data voltage of a to-be-displayed image is loaded to each data line, to input a corresponding data voltage to each sub-pixel, so as to realize image display of one display frame. Moreover, in in the blanking time phase of the at least one display frame, a gate-off voltage is loaded to a gate line(s) in the display panel, and a compensation voltage is loaded to each data line. This can solve the problem that when the display frequency of the display is switched from high frequency to low frequency, the brightness of the image displayed at the low frequency is increased compared with the image displayed at the high frequency, keep brightness stable, and improve display quality and view experience.
In the embodiments of the present disclosure, a display frame, in which a compensation voltage is loaded to a data line in the blanking time phase, is defined as a set display frame. As shown in
S100, in a data refresh phase of the set display frame, loading a gate-on voltage to a gate line in the display panel, and loading a data voltage of a to-be-displayed image to each data line, to input a corresponding data voltage to each sub-pixel.
S200, in a blanking time phase of the set display frame, loading a gate-off voltage to the gate line in the display panel, and loading a compensation voltage to each data line.
It should be noted that the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. In the embodiments of the present disclosure, a set display frame is designed among the plurality of continuous display frames. The set display frame has a data refresh phase and a blanking time phase. Here, in the data refresh phase, the gate-on voltage is loaded to a gate line(s) in the display panel, and the data voltage of the to-be-displayed image is loaded to each data line, so that a corresponding data voltage is input to each sub-pixel, thereby realizing image display of the display frame. In the blanking time phase, the gate-off voltage is loaded to the gate line(s) in the display panel, so as to control the transistor in each sub-pixel to be in an off state. Further, the compensation voltage is loaded to each data line, and when the data voltage in the sub-pixel connected with the data line is higher than the common electrode voltage, the compensation voltage loaded to the data line is lower than the data voltage in the sub-pixel connected with the data line. As shown in
Moreover, when the data voltage in the sub-pixel connected with the data line is lower than the common electrode voltage, the compensation voltage loaded on the data line is higher than the data voltage in the sub-pixel connected with the data line. As shown in
The rest are the same, so that the brightness of the sub-pixel can be reduced. In this way, when the display frequency is changed from high frequency to low frequency, by loading the compensation voltage to the data line, the brightness of the display image at low frequency can be reduced, so that the brightness of the display image at high frequency and the brightness of the display image at low frequency can be kept as stable as possible, improving display quality and view experience.
It should be noted that the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. Exemplarily, when the data voltage of the pixel electrode of the sub-pixel is greater than the common electrode voltage, the polarity of the sub-pixel can be positive. When the data voltage of the pixel electrode of the sub-pixel is lower than the common electrode voltage, the polarity of the sub-pixel can be negative. For example, in practical applications, the common electrode voltage on the common electrode can be 8V. Taking a sub-pixel as an example, if a voltage of 8V-12V is loaded to the pixel electrode of the sub-pixel, liquid crystal molecules at the sub-pixel can be for a positive polarity. Taking gray scales 0 to 255 as an example, the sub-pixel corresponds to a brightness of ±255 gray scales when a voltage of 12V is loaded to the pixel electrode. If a voltage of 4V-8V is loaded to the pixel electrode of the sub-pixel, liquid crystal molecules at the sub-pixel can be for a negative polarity. Taking gray scales 0 to 255 as an example, the sub-pixel corresponds to a brightness of −255 gray scales when a voltage of 4V is loaded to the pixel electrode.
In order to pursue a better display effect, for the control of liquid crystal molecules, a column inversion method or frame inversion method is used to improve the display effect of the liquid crystal molecules. In actual usage, the inversion of the liquid crystal molecules is driven by an electric field, so that its polarity is reversed. In the embodiments of the present disclosure, in order to improve the performance of the liquid crystal, the display panel may adopt the column inversion method. Exemplarily,
In the embodiments of the present disclosure, in order to improve the performance of the liquid crystal and reduce the power consumption, the display panel may adopt the frame inversion mode. Exemplarily,
In the following, description will be made by taking the column inversion mode of the display panel as an example.
In the embodiments of the present disclosure, the compensation voltage may include a first sub-compensation voltage. For each data line, a polarity corresponding to the first sub-compensation voltage loaded on the data line is opposite to a polarity corresponding to the sub-pixel connected with the data line. For example, as shown in
For example, as shown in
In the embodiments of the present disclosure, in two adjacent set display frames, for the same data line, the first sub-compensation voltage loaded on the data line in the previous set display frame and the common electrode voltage have a first difference therebetween. The first sub-compensation voltage loaded on the data line in the next set display frame and the common electrode voltage have a second difference therebetween. An absolute value of the first difference may be equal to an absolute value of the second difference. For example, as shown in
In the embodiments of the present disclosure, the compensation voltage may be fully loaded in the blanking time phase of at least one display frame. For example, as shown in
In the embodiments of the present disclosure, each display frame of the plurality of continuous display frames may be set as a set display frame. That is, in the data refresh phase included in each display frame of the plurality of continuous display frames, the gate-on voltage is loaded to the gate line(s) in the display panel, and the data voltage of the to-be-displayed image is loaded to each data line, to input a corresponding data voltage to each sub-pixel. And, in the blanking time phase included in each display frame of the plurality of continuous display frames, the gate-off voltage is loaded to the gate line(s) in the display panel, and the first sub-compensation voltage is loaded to each data line. This can compensate for each display frame, so that the brightness can be kept stable.
In the embodiments of the present disclosure, gray scales corresponding to compensation voltages applied to data lines can be the same. In this way, the gray scale of each compensation voltage can be determined without excessive calculation, and power consumption can be reduced. Exemplarily, the gray scales corresponding to the first sub-compensation voltage loaded to the data lines may be the same. In this way, the amount of calculation for determining the first sub-compensation voltage in different set display frames can be reduced, and the power consumption can be reduced. For example, the gray scale corresponding to the first sub-compensation voltage loaded on each data line is a gray scale 127. As shown in
As shown in
In the embodiments of the present disclosure, a voltage value of the compensation voltage may be a voltage value of any gray scale. Exemplarily, the voltage value of the first sub-compensation voltage may be a voltage value of any gray scale. For example, the gray scale corresponding to the first sub-compensation voltage loaded to each data line may be selected from 0 to 255 gray scales, for example, may be the gray scale 127 or the gray scale 200. Any gray scale here means that the same voltage of any gray scale can be added to the sub-pixels of the display panel that need to be compensated. The compensation method is simple, no additional compensation modules or operations are required, and power consumption is reduced. In practical applications, the gray scale can be selected according to the needs of practical applications, which is not limited herein.
In the embodiments of the present disclosure, for each data line, the gray scale corresponding to the compensation voltage loaded on the data line is the same as the gray scale corresponding to a data voltage in the sub-pixel connected with the data line. For example, for each data line, the gray scale corresponding to the first sub-compensation voltage loaded on the data line is the same as the gray scale corresponding to one data voltage in the sub-pixels connected with the data line. For example, the gray scale corresponding to the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray scale corresponding to the data voltage in the first row of sub-pixels in the first sub-pixel column. Or the gray scale corresponding to the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray scale corresponding to the data voltage in the first row of sub-pixels in the second sub-pixel column. Or the gray scale corresponding to the first sub-compensation voltage loaded on the data line corresponding to the first sub-pixel column may be the same as the gray scale corresponding to the data voltage in the last row of sub-pixels in the first sub-pixel column.
In the embodiments of the present disclosure, the blanking time phase of the set display frame may also be partially loaded with the first compensation voltage, for example, the blanking time phase may have at least one compensation phase, and the first sub-compensation voltage is loaded to the data line in the compensation phase. Exemplarily, as shown in
In the embodiments of the present disclosure, in the case that the blanking time phase of the set display frame has the plurality of compensation stages, an interval between every two adjacent compensation stages is the same. In this way, the compensation voltage can be evenly loaded to the data line in the blanking time phase.
In the embodiments of the present disclosure, the duration of the compensation phase satisfies a relationship: 0<tc<1/2tb. Here, tc represents a duration of the compensation phase, and tb represents a duration of the blanking time phase. In this way, only a part of the blanking time phase can be used as a compensation phase, so as to prevent the voltage loaded on the data line from flowing back into the sub pixels due to transistor leakage, thereby affecting the brightness of the sub pixels.
In the embodiments of the present disclosure, a boundary of the compensation phase may coincide with a boundary of the data refresh phase. Alternatively, a certain period of time may be set between the boundary of the compensation phase and the boundary of the data refresh phase.
With reference to
In the display frame F1, in the data refresh phase TS, when the signal ga1 has a gate-on voltage, the transistors 01 in the first row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DA1, the corresponding data voltage da2 is loaded to the data line DA2 and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the first row of sub-pixels. When the signal ga2 has a gate-on voltage, the transistors 01 in the second row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DAL, the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the second row of sub-pixels. When the signal ga3 has a gate-on voltage, the transistors 01 in the third row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DA1, the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the third row of sub-pixels. When the signal ga4 has a gate-on voltage, the transistors 01 in the fourth row of sub-pixels can be controlled to be turned on, the corresponding data voltage da1 is loaded to the data line DAL, the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the fourth row of sub-pixels. The rest of rows are deduced in the same way, and will not be repeated herein.
In the blanking time phase TB, the gate-off voltage is simultaneously loaded to the gate lines in the display panel, so as to control the transistor 01 in each sub-pixel to be in an off state. A voltage corresponding to the gray scale 127 is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and loaded to the data line corresponding to the first sub-pixel column. A voltage corresponding to the gray scale 127 is selected from 8V-12V as the first sub-compensation voltage corresponding to the positive polarity, and loaded to the data line corresponding to the second sub-pixel column. A voltage corresponding to the gray scale 127 is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and loaded to the data line corresponding to the third sub-pixel column. A voltage corresponding to the gray scale 127 is selected from 8V-12V as the first sub-compensation voltage corresponding to the positive polarity, and loaded to the data line corresponding to the fourth sub-pixel column.
In the display frame F2, in the data refresh phase TS, when the signal ga1 has a gate-on voltage, all the transistors 01 in the first row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DA1, the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the first row of sub-pixels. When the signal ga2 has a gate-on voltage, all the transistors 01 in the second row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DA1, the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the second row of sub-pixels. When the signal ga3 has a gate-on voltage, all the transistors 01 in the third row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DA1, the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the third row of sub-pixels. When the signal ga4 has a gate-on voltage, all the transistors 01 in the fourth row of sub-pixels can be controlled to be turned on, and the corresponding data voltage da1 is loaded to the data line DA1, and the corresponding data voltage da2 is loaded to the data line DA2, and the corresponding data voltage da3 is loaded to the data line DA3, so that the corresponding data voltage is input to the pixel electrode 02 in the fourth row of sub-pixels. The rest of rows are deduced in the same way, and will not be repeated herein.
In the blanking time phase TB, the gate-off voltage is simultaneously applied to the gate lines in the display panel, so as to control the transistor 01 in each sub-pixel to be in an off state. A voltage corresponding to the gray scale 127 is selected from 8V-12V as the first sub-compensation voltage corresponding to the positive polarity, and loaded to the data line corresponding to the first sub-pixel column. A voltage corresponding to the gray scale 127 is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and loaded to the data line corresponding to the second sub-pixel column. A voltage corresponding to the gray scale 127 is selected from 8V-12V as the first sub-compensation voltage corresponding to the positive polarity, and loaded to the data line corresponding to the third sub-pixel column. A voltage corresponding to the gray scale 127 is selected from 4V-8V as the first sub-compensation voltage corresponding to the negative polarity, and loaded to the data line corresponding to the fourth sub-pixel column.
Other display frames are deduced in the same way, and will not be described herein.
The embodiments of the present disclosure provide some other methods for driving the display panel, which are modified with respect to the implementation manners in the above-mentioned embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, the compensation voltage may further include a transition compensation voltage that appears before the first sub-compensation voltage. Moreover, when the data voltage in the sub-pixels connected with the data line is higher than the common electrode voltage, the transition compensation voltage loaded on the data line is lower than the data voltage in the sub-pixels connected with the data line. When the data voltage in the sub-pixels connected with the data line is lower than the common electrode voltage, the transition compensation voltage loaded on the data line is greater than the data voltage in the sub-pixels connected with the data line.
In the embodiments of the present disclosure, for each data line, the polarity corresponding to the transition compensation voltage loaded on the data line is the same as the polarity corresponding to the sub-pixels connected with the data line. For example, as shown in
For example, as shown in
Embodiments of the present disclosure further provide some methods for driving the display panel, which are modified for the implementation manners in the above embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, the following formula may also be used to determine the gray scale corresponding to the compensation voltage:
Here, VS11 represents the gray scale corresponding to the compensation voltage, VA11 represents the maximum gray scale in a display frame selected from the plurality of continuous display frames, and VA12 represents the minimum gray scale in the display frame selected from the plurality of continuous display frames, and VA11+VA12 is an even number.
Exemplarily, for example, VS11 may represent the gray scale corresponding to the first sub-voltage in the compensation voltage, so the gray scale of the first sub-compensation voltage may be determined by VS11=(VA11+VA12)/2.
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame. For example, as shown in
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be the set display frame. For example, as shown in
It should be noted that the rest of the working process of the method for driving the display panel corresponding to the embodiments may be basically the same as the rest of the working process of the method for driving the display panel in the above-mentioned embodiments, and will not be repeated herein.
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
In the embodiments of the present disclosure, the following formula may also be used to determine the gray scale corresponding to the compensation voltage:
Here, VS21 represents the gray scale corresponding to the compensation voltage, VA21 represents the maximum gray scale in the display frame selected from the plurality of continuous display frames, and VA22 represents the minimum gray scale in the display frame selected from the plurality of continuous display frames, and VA21+VA22 is an odd number.
Exemplarily, for example, VS21 may represent the gray scale corresponding to the first sub-voltage in the compensation voltage, so the gray scale of the first sub-compensation voltage may be determined by VS21=(VA21+VA22+1)/2.
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame. For example, as shown in
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be the set display frame. For example, as shown in
It should be noted that the rest of the working process of the method for driving the display panel corresponding to the embodiments may be basically the same as the rest of the working process of the method for driving the display panel in the above-mentioned embodiments, and will not be repeated herein.
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, loading the compensation voltage to each data line may include: in the blanking time phase of the set display frame, selecting a display frame from the plurality of display frames, and for each data line, loading a voltage of a gray scale, corresponding to a data voltage input into a row of sub-pixels of the display panel in the selected display frame, to the data line.
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame.
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be the set display frame.
In the embodiments of the present disclosure, loading the compensation voltage to each data line may include: in the blanking time phase of the set display frame, selecting a display frame from the plurality of display frames, and for each data line, loading a voltage of a gray scale, corresponding to a data voltage input into a first row of sub-pixels of the display panel in the selected display frame, to the data line to serve as the first sub-compensation voltage. For example, taking a display panel with four rows of sub-pixels as an example (of course, in practical applications, the number of rows of sub-pixels in a display panel is not only four, which can be determined according to actual conditions, and not limited herein), in combination with
In the embodiments of the present disclosure, loading the compensation voltage to each data line may include: in the blanking time phase of the set display frame, selecting a display frame from a plurality of display frames, and for each data line, loading a voltage of a gray scale, corresponding to a data voltage input into a middle row of sub-pixels of the display panel in the selected display frame, to the data line, where the voltage is taken as the first sub-compensation voltage. For example, taking a display panel with four rows of sub-pixels as an example (of course, in practical applications, the number of rows of sub-pixels in a display panel is not only four, which can be determined according to actual conditions, and is not limited herein), in combination with
In the embodiments of the present disclosure, loading the compensation voltage to each data line may include: in the blanking time phase of the set display frame, selecting a display frame from the plurality of display frames, and for each data line, loading a voltage of a gray scale, corresponding to a data voltage input into a last row of sub-pixels of the display panel in the selected display frame, to the data line, where the voltage is taken as the first sub-compensation voltage. For example, taking a display panel with four rows of sub-pixels as an example (of course, in practical applications, the number of rows of sub-pixels in a display panel is not only four, which can be determined according to actual applications, and is not limited herein), in combination with
It should be noted that the rest of the working process of the method for driving the display panel corresponding to this embodiment may be basically the same as the rest of the working process of the method for driving the display panel in the above-mentioned embodiments, and will not be repeated herein.
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, loading the compensation voltage to each data line may include: in the blanking time phase of a set display frame, selecting a display frame from the plurality of display frames, and for each data line, sequentially loading a voltage of a gray scale, corresponding to a data voltage input into the data line in the selected display frame, to the data line. In this way, the selection of the compensation voltage can be more diversified, and the compensation can be made more detailed.
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be a previous display frame adjacent to the set display frame. For example, taking a display panel with four rows of sub-pixels as an example (of course, in practical applications, the number of rows of sub-pixels in a display panel is not only four, which can be determined according to actual applications, and is not limited herein), in combination with
In the display frame F1, the data voltage input to the sub-pixels in the first row and second column corresponds to the gray scale 127, the data voltage input to the sub-pixels in the second row and second column corresponds to the gray scale 159, and the data voltage input to the sub-pixels in the third row and second column corresponds to the gray scale 160, and the data voltage input to the sub-pixels in the fourth row and second column corresponds to the gray scale 68. Then in the compensation stage of the display frame F2, a data line electrically connected with the second column of sub-pixels is sequentially input with the first sub-compensation voltage corresponding to the gray scale 127, the first sub-compensation voltage corresponding to the gray scale 159, the first sub-compensation voltage corresponding to the gray scale 160, and the first sub-compensation voltage corresponding to the gray scale 68, and the polarity corresponding to the first sub-compensation voltages input in the data line electrically connected to the second column in the display frame F2 is opposite to the polarity corresponding to the data voltage input to the second column of sub-pixels in the display frame F2, for example, the first sub-compensation voltages input in the data line both are negative polarity.
In the display frame F1, the data voltage input to the sub-pixels in the first row and third column corresponds to the gray scale 140, the data voltage input to the sub-pixels in the second row and third column corresponds to the gray scale 130, and the data voltage input to the sub-pixels in the third row and third column corresponds to the gray scale 40, and the data voltage input to the sub-pixels in the fourth row and third column corresponds to the gray scale 175. Then in the compensation stage of the display frame F2, a data line electrically connected with the third column of sub-pixels is sequentially input with the first sub-compensation voltage corresponding to the gray scale 140, the first sub-compensation voltage corresponding to gray scale 130, the first sub-compensation voltage corresponding to the gray scale 40, and the first sub-compensation voltage corresponding to the gray scale 175, and the polarity corresponding to the first sub-compensation voltages input in the data line electrically connected with the third column in the display frame F2 is opposite to the polarity corresponding to the data voltage input to the third column of sub-pixels in the display frame F2, for example, the first sub-compensation voltages input in the data line both are positive polarity.
In the display frame F1, the data voltage input to the sub-pixels in the first row and fourth column corresponds to the gray scale 177, the data voltage input to the sub-pixels in the second row and fourth column corresponds to the gray scale 129, and the data voltage input to the sub-pixels in the third row and fourth column corresponds to the gray scale 80, and the data voltage input to the sub-pixels in the fourth row and fourth column corresponds to the gray scale 198. Then in the compensation stage of the display frame F2, a data line electrically connected with the fourth column of sub-pixels is sequentially input with the first sub-compensation voltage corresponding to the gray scale 177, the first sub-compensation voltage corresponding to the gray scale 129, the first sub-compensation voltage corresponding to the gray scale 80, and the first sub-compensation voltage corresponding to the gray scale 198, and the polarity corresponding to the first sub-compensation voltages input in the data line electrically connected with the fourth column in the display frame F2 is opposite to the polarity corresponding to the data voltage input to the fourth column of sub-pixels in the display frame F2, for example, the first sub-compensation voltages input in the data line both are negative polarity.
In the embodiments of the present disclosure, the display frame selected from the plurality of display frames may be the set display frame. For example, taking a display panel with four rows of sub-pixels as an example (of course, in practical applications, the number of rows of sub-pixels in a display panel is not only four, which can be determined according to actual applications, and is not limited herein), in combination with
In the display frame F2, the data voltage input to the sub-pixels in the first row and second column corresponds to the gray scale 127, the data voltage input to the sub-pixels in the second row and second column corresponds to the gray scale 159, and the data voltage input to the sub-pixels in the third row and second column corresponds to the gray scale 160, and the data voltage input to the sub-pixels in the fourth row and second column corresponds to the gray scale 68. Then in the compensation stage of the display frame F2, a data line electrically connected with the second column of sub-pixels is sequentially input with the first sub-compensation voltage corresponding to the gray scale 127, the first sub-compensation voltage corresponding to the gray scale 159, the first sub-compensation voltage corresponding to the gray scale 160, and the first sub-compensation voltage corresponding to the gray scale 68, and the polarity corresponding to the first sub-compensation voltages input in the data line electrically connected with the second column in the display frame F2 is opposite to the polarity corresponding to the data voltage input to the second column of sub-pixels in the display frame F2, for example, the first sub-compensation voltages input in the data line both are negative polarity.
In the display frame F2, the data voltage input to the sub-pixels in the first row and third column corresponds to the gray scale 140, the data voltage input to the sub-pixels in the second row and third column corresponds to the gray scale 130, and the data voltage input to the sub-pixels in the third row and third column corresponds to the gray scale 40, and the data voltage input to the sub-pixels in the fourth row and third column corresponds to the gray scale 175. Then in the compensation stage of the display frame F2, a data line electrically connected with the third column of sub-pixels is sequentially input with the first sub-compensation voltage corresponding to the gray scale 140, the first sub-compensation voltage corresponding to the gray scale 130, the first sub-compensation voltage corresponding to the gray scale 40, and the first sub-compensation voltage corresponding to the gray scale 175, and the polarity corresponding to the first sub-compensation voltages input in the data line electrically connected with the third column in the display frame F2 is opposite to the polarity corresponding to the data voltage input to the third column of sub-pixels in the display frame F2, for example, the first sub-compensation voltages input in the data line both are positive polarity.
In the display frame F2, the data voltage input to the sub-pixels in the first row and fourth column corresponds to the gray scale 177, the data voltage input to the sub-pixels in the second row and fourth column corresponds to the gray scale 129, and the data voltage input to the sub-pixels in the third row and fourth column corresponds to the gray scale 80, and the data voltage input to the sub-pixels in the fourth row and fourth column corresponds to the gray scale 198. Then in the compensation stage of the display frame F2, a data line electrically connected with the fourth column of sub-pixels is sequentially input with the first sub-compensation voltage corresponding to the gray scale 177, the first sub-compensation voltage corresponding to the gray scale 129, the first sub-compensation voltage corresponding to the gray scale 80, and the first sub-compensation voltage corresponding to the gray scale 198, and the polarity corresponding to the first sub-compensation voltages input in the data line electrically connected with the fourth column in the display frame F2 is opposite to the polarity corresponding to the data voltage input to the fourth column of sub-pixels in the display frame F2, for example, the first sub-compensation voltages input in the data line both are negative polarity.
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, a part of the plurality of continuous display frames is set display frames. Furthermore, among the plurality of continuous display frames, the display frames other than the set display frame are non-set display frames. That is, a part of the plurality of continuous display frames is set display frames, and the rest of the display frames are non-set display frames.
In the embodiments of the present disclosure, non-set display frames include:
It should be noted that the floating connection of each data line in the blanking time phase may mean that no voltage is applied to each data line.
That is, the working process of the data refresh stage in the non-set display frame is basically the same as the working process of the data refresh stage in the set display frame. However, no compensation phase is set in the blanking time phase in the non-set display frame.
In the embodiments of the present disclosure, there may be at least one non-set display frame between two adjacent set display frames. For example, there may be a non-set display frame between two adjacent set display frames. It is also possible to have two non-set display frames between two adjacent set display frames. It is also possible to have three non-set display frames between two adjacent set display frames. For example, as shown in
In the embodiments of the present disclosure, the number of non-set display frames between every two adjacent set display frames may be the same. For example, there may be a non-set display frame between every two adjacent set display frames. It is also possible to have two non-set display frames between every two adjacent set display frames. It is also possible to have three non-set display frames between every two adjacent set display frames. For example, as shown in
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, the compensation voltage may include a second sub-compensation voltage; for each data line, the polarity corresponding to the second sub-compensation voltage loaded on the data line is the same as the polarity corresponding to the sub-pixel connected with the data line. For example, as shown in
As shown in
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
In the embodiments of the present disclosure, as shown in
In the embodiments of the present disclosure, at each display frequency that the display can adopt, as shown in
Embodiments of the present disclosure provide still some methods for driving the display panel, which are modified with respect to the implementation manners in the above-mentioned embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated herein.
When the data voltage in the sub-pixels connected with the data line is higher than the common electrode voltage, the compensation voltage loaded on the data line may also be higher than the data voltage in the sub-pixels connected with the data line. When the data voltage in the sub-pixels connected with the data line is lower than the common electrode voltage, the compensation voltage loaded on the data line may also be lower than the data voltage in the sub-pixels connected with the data line. In this way, the voltage difference between the source and the drain of the transistor in the sub-pixel can be reduced during the blanking time, and the leakage of the transistor can be reduced. In this way, when the display is continuously at a low display frequency, by reducing the leakage of the transistor, the data voltage input to the sub-pixel can be kept stable, thereby avoiding the problem that the brightness of the display screen decreases when the display is continuously at a low display frequency.
Embodiments of the present disclosure further provide a display drive circuit. The display panel works in a plurality of continuous display frames, and each display frame includes a data refresh phase and a blanking time phase; and the display drive circuit is configured for:
It should be noted that the working principle and specific implementation of the display drive circuit are the same as those of the method for driving the display panel in the above-mentioned embodiments. Therefore, the working method of the display drive circuit can be implemented by referring to the specific implementation manner of the method for driving the display panel in the above-mentioned embodiments, and it will not be repeated herein.
Embodiments of the present disclosure further provides a display device, as shown in
In the embodiments of the present disclosure, as shown in
The timing controller 200 is configured to: in a data refresh phase of at least one of a plurality of continuous display frames, input a first gate drive signal to the gate drive circuit 120, and input a first source drive signal to the source drive circuit. The gate drive circuit 120 is configured to load a gate-on voltage to gate lines GA1 to GA5 in the display panel 100 according to the received first gate drive signal. The source drive circuit 110 is configured to load a data voltage of a to-be-displayed image to each of the data lines DA1 to DA6 according to the received first source drive signal, so as to realize the image display of one display frame.
The timing controller 200 is configured to: in a blanking time phase of the at least one display frame, input a second gate drive signal to the gate drive circuit 120, and input a second source drive signal to the source drive circuit 110. The gate drive circuit 120 is configured to load a gate-off voltage to the gate lines GA1 to GA5 in the display panel according to the received second gate drive signal. The source drive circuit 110 is configured to load a compensation voltage to each of the data lines DA1 to DA6 according to the received second source drive signal. Here, when the data voltage in the sub-pixel connected with the data line is greater than the common electrode voltage, the compensation voltage loaded on the data line is lower than the data voltage in the sub-pixel connected with the data line; when the data voltage in the sub-pixel connected with the data line is lower than the common electrode voltage, the compensation voltage loaded on the data line is greater than the data voltage in the sub-pixels connected with the data line. Therefore, the problem of increased brightness of the display screen when the display frequency of the display changes from high frequency to low frequency can solve, thereby keeping the brightness stable, and improving display quality and view experience.
It should be noted that the working principle and specific implementation of the display device are the same as those of the method for driving the display panel in the above-mentioned embodiments. Therefore, the working method of the display device can be implemented by referring to the specific implementation manner of the method for driving the display panel in the above-mentioned embodiments, and it will not be repeated herein.
During specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated herein, nor should they be used as limitations on the present disclosure.
In the method for driving the display panel, the display drive circuit, and the display device provided by the embodiments of the present disclosure, in the data refresh phase of a set display frame among the plurality of continuous display frames, a gate-on voltage is time-divisionally loaded on a gate line in the display panel, and when the gate-on voltage is loaded to each gate line, a data voltage of a to-be-displayed image is loaded to each data line, so that the corresponding data voltage is input to each sub-pixel, so as to realize the image display of one display frame. Moreover, in the blanking time phase of the set display frame, the gate-off voltage is simultaneously loaded to the gate lines in the display panel, and the compensation voltage is loaded to each data line. As such, the voltage difference between the source and the drain of the transistor in the blanking time phase can reduce, thereby reducing the leakage of the sub-pixel and improving the display quality and view experience.
Those skilled in the art should understand that the embodiments of the present disclosure may be provided as a method, a system, or a computer program product. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to a disk storage, a CD-ROM, an optical storage, etc.) having an computer-usable program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, a special purpose computer, an embedded processor, or a processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a an apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction devices, the instruction device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thus the instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.
While preferred embodiments of the disclosure have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the disclosure.
Apparently, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. In this way, if the modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure also intends to include these modifications and variations.
This application is a national phase entry under 35 U.S.C § 371 of International Application No. PCT/CN2021/121618, filed on Sep. 29, 2021, the entire content of which is incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/121618 | 9/29/2021 | WO |
