1. Field of the Invention
The present invention relates to a method for driving a plasma display panel.
2. Description of the Related Background Art
Plasma display panels of AC type (alternating-current discharge type) have recently been put into production as thin-model displays. A plasma display panel contains two substrates, i.e., a front glass substrate and a rear glass substrate which are opposed to each other with a predetermined gap therebetween. A plurality of pairs of row electrodes which are paired with each other and extended in parallel are formed on the inner surface (the side opposed to the rear glass substrate) of the foregoing front glass substrate, or a display surface, as pairs of sustain electrodes. A plurality of column electrodes are formed on the rear glass substrate as address electrodes so as to extend orthogonal to the pairs of row electrodes, and phosphors are further applied thereto. When viewed from the foregoing display-surface side, display cells corresponding to pixels are formed at intersections of the pairs of row electrodes and the column electrodes.
The plasma display panel is subjected to gradation driving based on a sub-field method for the sake of achieving halftone display luminance corresponding to an input video signal.
In the gradation driving based on the sub-field method, a display drive for a single field of a video signal is performed in a plurality of individual sub-fields to which respective intended numbers of times (or periods) of light emission are assigned. In each sub-field, an address stage and a sustain stage are performed in succession. At the address stage, selective discharge is generated between the row electrodes and the column electrodes of respective display cells selectively in accordance with the input video signal, thereby forming (or erasing) a predetermined amount of wall charge. At the sustain stage, sustain pulses are applied to each row electrode so that display cells having the predetermined amount of wall charge formed therein alone generate discharge repeatedly to sustain the light-emitting state resulting from the discharge. An initialization stage is also performed at least in the first sub-field, prior to the address stage. In the initialization stage, reset discharge is generated between the paired row electrodes in all the display cells, thereby initializing the amount of wall charge remaining in each display cell.
The reset discharge is comparatively strong and not involved in the content of an image to be displayed, so that light emission caused by the reset discharge lowers the image contrast.
In such a situation, a proposal has been made on a PDP and driving method for same that discharge delay is reduced by putting a magnesium oxide crystallization, that emits light of cathode-luminescence with a peak at a wavelength of 200-300 nm under the excitation of electron beam irradiation, over the surface of a dielectric layer covering the row electrode pairs (see Japanese Patent Laid-Open No. 2006-54160). According to the PDP, weak discharge can be caused stably because the post-discharge priming effect continues for a comparatively long time. Consequently, by applying to the PDP row electrodes a reset pulse having a pulse waveform whose voltage gradually reaches a peak value with the passage of time, weak reset discharge is caused between adjacent ones of the row electrodes. In this case, the image contrast can be improved because the luminance level of light emission given by the discharge is lowered by the weakening of reset discharge.
However, with such a driving scheme, there is a difficulty in fully enhancing so-called dark contrast in displaying a dark image, thus problematically making it impossible to provide a dark image in a quality state.
It is an object of the present invention to provide a plasma display panel driving method capable of enhancing representability with luminance gradations in displaying a dark image.
A plasma display panel driving method in the invention is a method for driving a plasma display panel in accordance with pixel data for each pixel based on a video signal, the plasma display panel having first and second substrates which are oppositely arranged sandwiching a discharge space in which discharge gas is filled, a plurality of row electrode pairs formed on the first substrate and each providing a scanning line, and a plurality of column electrode formed on the second substrate, in order to form display cells each including a phosphor layer at intersections of the row electrode pairs and the column electrodes, the method comprising the steps of: executing a reset stage for initializing the display cells in a beginning sub-field of a plurality of sub-fields into which a one-field display period of the video signal is divided; executing, in order, an address stage for setting the display cells in an ON mode or OFF mode by causing an address discharge selectively in the display cells in accordance with the pixel data in all of the plurality of sub-fields, and a sustain stage for causing a sustain discharge in each display cell set in the ON mode; and executing an erase stage for setting the OFF mode for all display cells which are in the ON mode-following the sustain stage of an end sub-field of the plurality of sub-fields, wherein, in the erase stage, a scanning pulse is sequentially applied to one row electrode of each of the row electrode pairs for each scanning line or for each scanning line group which is formed by a plurality of scanning lines, while an erase pulse is applied to the column electrodes simultaneously with the application of the scanning pulse, to cause an erase discharge between the one row electrode and each of the column electrodes to which the erase pulse is applied.
In the plasma display panel driving method according to the invention, the erase pulse is applied for each scanning line or for each scanning line group in the erase period of the last sub-field of a one-field display period, thus preventing a large current from flowing instantaneously and a pulse waveform from distorting. Thus, erase discharge is positively effected in the display cell holding an ON mode in the last sub-field. After terminating the erase stage of the last sub-field, all the display cells are placed in an OFF mode. This, accordingly, can improve the representability with luminance gradations in displaying a dark image.
With referring to the drawings, explanation will be now made on embodiments according to the present invention.
The plasma display apparatus comprises a plasma display panel or PDP 50, an X-electrode driver 51, a Y-electrode driver 53, an addressing driver 55 and a drive control circuit 56, as shown in
In the PDP 50, column electrodes D1 to Dm are extended and arranged in the longitudinal direction (vertical direction) of a two-dimensional display screen, and row electrodes X1 to Xn and row electrodes Y1 to Yn are extended and arranged in the lateral direction (the horizontal direction) thereof. The row electrodes X1 to Xn and row electrodes Y1 to Yn form row electrodes pairs (Y1, X1), (Y2, X2) , (Y3, X3), . . . , (Yn, Xn) which are paired with those adjacent to each other and which serve as the first display line to the nth display line in the PDP 50. In each intersection part of the display lines with the column electrodes D1 to Dm (areas surrounded by dashed lies in
As shown in
A magnesium oxide layer 13 is formed on a surface of the dielectric layer 12 including the layer portion 12A. The magnesium oxide layer 13 contains a magnesium oxide crystal (hereinafter, referred to as CL-emission MgO crystallization) serving as a secondary-electron emission material to cause CL (cathode luminescence) emission having a peak at a wavelength of 200-300 nm, particularly 230-250 nm, when excited with the illumination of an electronic ray. The CL-emission MgO crystallization is obtainable by the vapor phase oxidation of a magnesium vapor produced by heating magnesium, which has a polycrystal structure that cubic crystals are compacted together or a cubic single-crystal structure, for example. The CL-emission MgO crystallization has a mean grain size of 2000 angstroms or greater (measurement result by the BET method).
In order to form a magnesium-oxide single crystal having the mean grain size as great as 2000 angstroms or greater by a vapor phase process, there is a need to increase the heating temperature for producing a magnesium vapor. This increases the flame length for causing magnesium and oxide to react. As the vapor-phase-oxidized magnesium single crystal increases in grain size with the increasing temperature difference between the flame and the surrounding, those can be formed greater in the number having an energy level corresponding to the peak wavelength (e.g. around 235 nm, within 230-250 nm) of CL emission as mentioned above.
The energy level corresponding to the CL-emission peak wavelength is provided for the vapor-phase-oxidized magnesium single crystal produced by reacting the greater quantity of oxygen through increasing the amount of magnesium to vaporize per unit time and increasing the reaction area of magnesium with oxygen, as compared to the usual vapor-phase oxidation.
By attaching the CL-emission MgO crystallization to the surface of the dielectric layer 12 by spraying, electrostatic application or so, the magnesium oxide layer 13 is formed. Alternatively, by forming a thin-film magnesium oxide layer on the surface of the dielectric layer 12 by evaporation or sputtering, CL-emission MgO crystallization may be attached thereto thereby forming the magnesium oxide layer 13.
On a back substrate 14 arranged parallel with the front transparent substrate 10, column electrodes D are formed extending orthogonally to the row electrode pairs (X, Y), in a position opposed to the transparent electrodes Xa, Ya of the row electrode pair (X, Y). Over the back substrate 14, a column-electrode protection layer 15 white in color is further formed covering the column electrodes D. Barriers 16 are formed on the column-electrode protection layer 15. The barrier 16 is formed in a ladder form with a transverse wall 16A extending transversely of the two-dimensional display screen and a longitudinal wall 16B extending lengthwise of the two-dimensional display screen intermediately between the adjacent column electrodes D, in a position corresponding to the bus electrodes Xb, Yb of the row electrode pair (X, Y). Furthermore, the ladder-formed barrier 16 as shown in
Incidentally, the phosphor layer 17 contains an MgO crystallization (including a CL-emission MgO crystallization) as a secondary-electron emission material, in a form as shown in
Here, the discharge space S of the display cell PC and the gap SL are closed from each other by providing the magnesium oxide layer 13 in contact with the transverse wall 16A, as shown in
The drive control circuit 56 first converts the input video signal into 8-bit pixel data which expresses its luminance levels in 256 tone levels pixel by pixel, and performs multi-gradation processing consisting of error diffusion processing and dither processing to the pixel data. Namely, firstly, in the error diffusion processing, the high-order six bits of the pixel data are taken as display data while the remaining low-order two bits are as error data. By reflecting the display data with the weighted addition of the error data concerning the pixel data corresponding to surrounding pixels, 6-bit error-diffusion pixel data is obtained. With such error diffusion, the low-order two bits of luminance on one pixel is synthetically represented by pixels surrounding the one pixel. Therefore, gray-scale representation is available equivalently to 8-bit pixel data, by means of 6-bit display data smaller than 6-bit one. Then, the drive control circuit 56 performs dithering on the error-diffused pixel data obtained by the 6-bit error diffusion. In dithering, by taking a plurality of mutually adjacent pixels as one pixel unit, dither coefficients different one from another are assigned and added to the respective ones of error-diffused pixel data corresponding to the pixels of one pixel unit, thereby obtaining dither-added pixel data. With such addition of dither coefficients, gradation representation is available correspondingly to 8 bits by use of only the high-order four bits of the dither-added pixel data. For this reason, the drive control circuit 56 converts the high-order four bits of the dither-added pixel data into 4-bit multi-gradation pixel data PD, that every luminance level is to be represented with 15 levels, as shown in
Furthermore, the drive control circuit 56 supplies various control signals for driving the PDP 50 configured as above to a panel driver, formed by the X-electrode driver 51, the Y-electrode driver 53 and the address driver 55, according to an emission-drive sequence as shown in
The panel driver, i.e. X-electrode driver 51, Y-electrode driver 53 and address driver 55, generates various drive pulses as shown in
At first, in the former half of the reset stage R of the sub-field SF1, the Y-electrode driver 53 applies to all the row electrodes Y1-Yn a positive reset pulse RPY1 having a waveform moderate in potential transition at the leading edge with respect to the passage of time as compared to that of a sustain pulse, referred later. The reset pulse RPY1 has a peak potential higher than the peak potential of the sustain pulse. In this duration, the address driver 55 sets the column electrodes D1-Dm at a ground potential (0 volt) In response to the application of the reset pulse RPY1, first reset discharge takes place between the row electrode Y and the column electrode D in each of all the display cells PC. Namely, in the former half of the reset stage R, applying a voltage between the both electrodes such that the row electrode Y is on the anode side and the column electrode D on the cathode side, discharge is caused as a first reset discharge to flow a current from the row electrode Y to the column electrode D (hereinafter, referred to as cathode-at-column discharge). In response to the first reset discharge, negative wall charges are formed nearby the row electrode Y in each of all the display cells PCs while positive wall charges are nearby the column electrode D.
In the former half of the reset stage R, the X-electrode driver 51 applies to all the row electrodes X1-Xn a reset pulse RPx same in polarity as the reset pulse RPY1 and having a peak potential capable of preventing a discharge from occurring between the row electrodes X and Y due to the application of the reset pulse RPY1.
In the latter half of the reset stage R of the sub-field SF1, the Y-electrode driver 53 generates a negative reset pulse RPY2 that is moderate in potential transition at the leading edge with respect to the passage of time and applies it to all the row electrodes Y1-Yn. Furthermore, in the latter half of the reset stage R, the X-electrode driver 51 applies a positive base pulse BP+ having a predetermined base potential to all the row electrodes X1-Xn. On this occasion, second reset discharge is caused between the row electrodes X and Y in all the display cells PCs by the application of the negative reset pulse RPY2 and positive base pulse BP+. The reset pulse RPY2 and the base pulse BP+ each have a peak potential provided minimally to positively cause a second reset discharge between the row electrodes X and Y in consideration of the wall charges formed nearby the row electrodes X and Y in response to the first reset discharge. The reset pulse RPY2 is set with a negative peak potential higher in value than the peak potential of the negative write scanning pulse SPw referred later, i.e. at a potential approximate to 0 volt. Namely, this is because, if providing the peak potential of the reset pulse RPY2 lower than the peak potential of the write scanning pulse SPw, strong discharge results between the row electrode Y and the column electrode D to thereby significantly erase the wall charges formed nearby the column electrode D and hence make unstable the address discharge in the selective write-address stage Ww. By the second reset discharge caused in the latter half of the reset stage R, erased are the wall charges that have been formed nearby the row electrodes X, Y in each of the display cells PCs, thus initializing all the display cells PCs in the OFF mode. Furthermore, in response to the application of the reset pulse RPY2, weak discharge is also caused between the row electrode Y and the column electrode D in all the display cells PCs. Due to the discharge, the positive wall charges formed nearby the column electrode D are partly erased away thus being regulated into the amount that selective write-address discharge is to be caused correctly in the selective write-address stage Ww.
In the selective write-address stage Ww of the sub-field SF1, the Y-electrode driver 53 applies a write scanning pulse SPw having a negative peak potential selectively, in order, to the row electrodes Y1-Yn while simultaneously applying to the row electrodes Y1-Yn a negative base pulse BP− having a predetermined base potential as shown in
In the selective write-address stage Ww, the address driver 55 converts the pixel-drive data bit corresponding to the sub-field SF1 into a pixel data pulse DP having a pulse voltage commensurate with the logic level thereof. For example, when supplied with pixel-drive data bit having a logic level 1 to set the display cell PC in the ON mode, the address driver 55 converts it into a pixel-data pulse DP having a positive peak potential. On the other hand, for pixel-drive data bit having a logic level 0 to set the display cell PC in the OFF mode, it is converted into a pixel-data pulse DP having a low voltage (0 volt). The address driver 55 applies such pixel-data pulses DP in an amount of one display line (m in the number) per time to the column electrodes D1-Dm synchronously with the application timing of the write scanning pulses SPw. On this occasion, simultaneously with the write scanning pulse SPw, selective write-address discharge is caused between the column electrode D and the row electrode Y in the display cell PC to which a high-voltage pixel data pulse DP has been applied for setting into the ON mode. Immediately after the selective write-address discharge, weak discharge is also caused between the row electrodes X and Y of the relevant display cell PC. Namely, although a voltage commensurate with the base pulse BP− or BP+ is applied between the row electrodes X and Y after the application of the write scanning pulse SPw, the relevant voltage is set at a value lower than the discharge start voltage at the display cells PCs so that discharge is not to be caused in the display cell PC by only the application of that voltage. Nevertheless, when selective write-address discharge is caused, discharge arises between the row electrodes X and Y by the sole application of the voltage based on a base pulse BP−, BP+ due to the inducement of the selective write-address discharge. By such discharge together with the selective write-address discharge, the display cell PC is set in a state that positive wall charges are formed nearby the row electrode Y, negative wall charges are formed nearby the row electrode X and negative wall charges are formed nearby the column electrode D, i.e. in the ON mode. On the other hand, selective write-address discharge, like the above, is not caused between the column electrode D and the row electrode Y in the display cell PC to which applied are a pixel data pulse DP having a low voltage (0 volt) for setting into the OFF mode simultaneously with the write scanning pulse SPw, hence not causing a discharge between the row electrodes X and Y. Accordingly, the display cell remains in its state, i.e. in the OFF mode that initialization is made in the reset stage R.
In the sustain stage I of the sub-field SF1, the Y-electrode driver 53 generates a sustain pulse IP having positive peak potential in an amount of one pulse and applies it simultaneously to the row electrodes Y1-Yn. In this duration, the X-electrode driver 51 sets the row electrodes X1-Xn at a ground potential (0 volt) while the address driver 55 sets the column electrodes D1-Dm at a ground potential (0 volt). In response to the application of the sustain pulse IP, sustain discharge is caused between the row electrodes X and Y in the display cell PC being set in the ON mode. Due to the sustain discharge, the phosphor layer 17 gives off light toward the outside through the front transparent substrate 10, thus effecting once emission of display light correspondingly to the weight of luminance for the sub-field SF1. In response to the application of the sustain pulse IP, discharge is also caused between the row electrode Y and the column electrode D in the display cell PC being set in the ON mode. By such discharge together with the sustain discharge, negative wall charges are formed nearby the row electrode Y in the display cell PC while positive wall charges are formed nearby the row electrode X and the column electrode D. After the application of the sustain pulse IP, the Y-electrode driver 53 applies to the row electrodes Y1-Yn a wall-charge adjust pulse CP that is moderate in potential transition at the leading edge with respect to the passage of time and having a negative peak potential, as shown in
In the selective erase-address stage WD in each of the sub-fields SF2-SF14, the Y-electrode driver 53 applies an erase scanning pulse SPD having a negative peak potential as shown in
In the selective erase-address stage WD, the address driver 55 first converts the pixel-drive data bit corresponding to the relevant sub-field SF into a pixel-data pulse DP having a pulse voltage commensurate with the logic level thereof. For example, when supplied with pixel-drive data bit having a logic level 1 for transiting the display cell PC from ON to OFF mode, the address driver 55 converts it into a pixel-data pulse DP having a positive peak potential. When supplied with pixel-drive data bit having a logic level 0 for maintaining the display cell PC in its current status, it is converted into a pixel-data pulse DP having a low voltage (0 volt). The address driver 55 applies the pixel-data pulse DP in an amount of one display line (m in the number) per time, in order, to the column electrodes D1-Dm synchronously with the application timing of the erase scanning pulse SPD. On this occasion, selective erase-address discharge is caused between the column electrode D and the row electrode Y in the display cell PC to which the pixel-data pulse DP is applied simultaneously with the erase scanning pulse SPD. By the selective erase-address discharge, the relevant display cell PC is set in a state that positive wall charges are formed nearby the row electrodes Y and X while negative wall charges are nearby the column electrode D, i.e. in the OFF mode. On the other hand, such selective erase-address discharge is not caused between the column electrode D and the row electrode Y in the display cell PC to which a low-voltage (0 volt) pixel data pulse DP is applied simultaneously with the erase scanning pulse SPD. Accordingly, the relevant display cell PC remains in its state (in the ON mode or in the OFF mode).
In the sustain stage I of each of the sub-fields SF2-SF14, the X-electrode and Y-electrode drivers 51, 53 apply sustain pulses IP having a positive peak potential alternately to the row electrodes X1-Xn and Y1-Yn, repeatedly in the (even) number of times corresponding to the weighting of luminance for the relevant sub-field, as shown in
In the last erase stage E of the last sub-field SF14, the Y-electrode driver 53 applies an erase scanning pulse SPD′ having a negative peak potential as shown in
In the erase stage E, the address driver 55 applies an address pulse DP′ having a positive peak potential, as a erase pulse, in an amount of one display line (m in the number) per time to the column electrodes D1-Dm synchronously with the application timing of the erase scanning pulse SPD′ in order to put all the display cells PCs in erase mode, similarly to the case of supplying the pixel-drive data bit having a logic level 1. On this occasion, erase discharge is caused between the column electrode D and the row electrode Y, in all the display cells PCs that the address pulse DP′ is applied simultaneously with the erase scanning pulse SPD and staying in the ON mode. By the erase discharge, the display cell PC staying in the ON mode is set into a state that wall charges are formed positive nearby the row electrodes X, Y and negative nearby the column electrode D, i.e. in the OFF mode. In the display cell PC that have been placed in the OFF mode at or before the sub-field SF13, the OFF mode is maintained. This places all the display cells PCs in the OFF mode.
Such driving is executed based on fifteen patterns of pixel-drive data GD as shown in
With such driving, there are no light-emission-pattern (ON, OFF state) inverted regions coexistent on one screen within the one-field display period. Thus, false contour is prevented from occurring in such a state.
Here, in the
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
Referring to
On the other hand,
As shown in
Accordingly, in case cathode-at-column discharge is caused by applying, to the Y-electrode of the PDP 50, a reset pulse RPY1 having a waveform moderate in potential transition at a rise section as in
Namely, in the embodiment, cathode-at-column discharge having a weak intensity is caused by applying a reset pulse RPY1, say, as shown in
There is an effect that discharge probability is improved by the priming-particle release action from the secondary-electron emission material, particularly the CL-emission MgO material, of the phosphor layer 17. In the erase stage E, an erase pulse is simultaneously applied to all the display cells PCs, discharge occurs nearly simultaneously between the row electrode Y and the column electrode D in all the display cells PCs being in the ON mode. In such a case, because discharge occurs nearly simultaneously in a number of display cells PCs, a large current flows instantaneously. The large current distorts the waveform of the erase pulse with a result of a weakened erase discharge. In such a case, there possibly occur a display cell PC not to completely become an erase mode in respect of the wall charges. For such a disadvantage, by employing a structure that erasure is sequentially on a scanning-line-by-scanning-line basis (for each scanning line) as in the
As for the waveform at a rise of the rest pulse RPY1 to be applied to the row electrode Y in order to cause a reset discharge as a cathode-at column discharge, the inclination may gradually change with the passage of time, say, as shown in
The drive control circuit 56 converts the high-order four bits of the dither-added pixel data, obtained in the dithering, into 4-bit mult-gradation pixel data PDS representing every luminance with 16 levels as shown in
The panel driver, i.e. X-electrode driver 51, Y-electrode driver 53 and address driver 55, generates various drive pulses as shown in
At first, in the former half of the first reset stage R1 of the sub-field SF1, the Y-electrode driver 53 applies to all the row electrodes Y1-Yn a positive reset pulse RP1Y1 having a waveform moderate in potential transition at the leading edge with respect to the passage of time as compared to that of a sustain pulse to be generated in the sustain stage I. In this duration, the X-electrode driver 51 applies to all the row electrodes X1-Xn a reset pulse RP1x same in polarity as the reset pulse RPY1 and having a peak potential capable of preventing a surface discharge from occurring between the row electrodes X and Y upon the application of the rest pulse RP1Y1. In this duration, unless a surface discharge occurs between the row electrodes X and Y, the X-electrode driver 51 may set all the row electrodes X1-Xn at a ground potential (0 volt) instead of applying the reset pulse RP1x. Here, in the former half of the first reset stage R1, a weak first reset discharge is caused between the row electrode Y and the column electrode D in all the display cells PCs by the application of the reset pulse RP1Y1 as noted before. Namely, in the former half of the first reset stage R1, a cathode-at-column discharge is caused as a first reset discharge to flow a current from the row electrode Y to the column electrode D by applying a voltage between the both electrodes such that the row electrode Y is on the anode side and the column electrode D on the cathode side. In response to the first reset discharge, wall charges are formed negative nearby the row electrode Y and positive nearby the column electrode D in all the display cells PC.
In the latter half of the first reset stage R1 of the sub-field SF1, the Y-electrode driver 53 generates a negative reset pulse RP1Y2 that is moderate in potential transition at the leading edge with respect to the passage of time and applies it to all the row electrodes Y1-Yn. In this duration, the X-electrode driver 51 sets all the row electrodes X1-Xn at ground potential (0 volt). In the latter half of the first reset stage R1, second reset discharge is caused between the row electrodes X and Y in all the display cells PCs by the application of the reset pulse RP1Y2. The second reset discharge erases away the wall charges formed nearby the row electrodes X and Y in the display cells PCs, to initialize all the display cells PCs in the OFF mode. Furthermore, by the application of the reset pulse RP1Y2, weak discharge is caused between the row electrode Y and the column electrode D in all the display cells PCs. The weak discharge erases away part of the positive wall charges formed nearby the column electrode D and adjusts those into an amount to correctly cause a selective write-address discharge in the first selective write-address stage W1w, referred later.
In the first selective write-address stage W1w of the sub-field SF1, the Y-electrode driver 53 applies a write scanning pulse SPw having a negative peak potential selectively, in order, to the row electrode Y1-Yn while simultaneously applying to the row electrodes Y1-Yn a negative base pulse BP− having a predetermined base potential as shown in
Accordingly, in the first selective write-address stage W1w of the sub-field SF1, selective write-address discharge is caused only between the column electrode D and the row electrode Y in the display cell PC by the application of the write scanning pulse SPw and high-voltage pixel-data pulse DP. This sets the display cell PC in the ON mode that wall charges are formed positive nearby the row electrode Y and negative nearby the column electrode D despite no wall charges exist nearby the row electrode X. Meanwhile, selective write-address discharge, like the above, is not caused between the column electrode D and the row electrode Y in the display cell PC to which low-voltage (0 volt) pixel-data pulse DP is applied for setting into the OFF mode simultaneously with the write scanning pulse SPw. Accordingly, the relevant display cell PC remains in the OFF mode initialized in the first reset stage R1, i.e. in a state discharge is not to occur at neither of between the row electrode Y and the column electrode D nor between the row electrodes X and Y.
In the slight-emission stage LL of the sub-field SF1, the Y-electrode driver 53 applies a slight-emission pulse LP having a positive, predetermined peak potential as shown in
Further, as shown in
After the slight-emission discharge, wall charges are formed negative nearby the row electrode Y and positive nearby the column electrode D.
In the former half of the second reset stage R2 of the sub-field SF2, the Y-electrode driver 53 applies to all the row electrodes Y1-Yn a positive reset pulse RP2Y1 having a waveform moderate in potential transition at the leading edge with the passage of time as compared to that of the sustain pulse. The reset pulse RP2Y1 has a peak potential higher than the peak potential of the reset pulse RP1Y1. In this duration, the address driver 55 sets the column electrodes D1-Dm at a ground potential (0 volt) while the X-electrode driver 51 applies to all the row electrodes X1-Xn a positive reset pulse RP2X having a peak potential capable of preventing a surface discharge from occurring between the row electrodes X and Y due to the application of the reset pulse RP2Y1. Provided that a surface discharge does not occur between the row electrodes X and Y the X-electrode driver 51 may set all the row electrodes X1-Xn at ground potential (0 volt) instead of applying a reset pulse RP2X. By the application of the reset pulse RP2Y1, first reset discharge is caused weaker than the cathode-at-column discharge in the slight-emission stage LL, between the row electrode Y and the column electrode D in the display cell PC, that a cathode-at-column discharge has not been caused in the slight-emission stage LL, out of the display cells PCs. Namely, in the former half of the second reset stage R2, by applying a voltage between the both electrodes such that the row electrode Y is on the anode side and the column electrode D on the cathode side, cathode-at-column discharge is caused as the first reset discharge to flow a current from the row electrode Y to the column electrode D. In the display cell PC that slight-emission discharge has been already caused in the slight-emission stage LL, discharge is not caused even if the reset pulse RP2Y1 is applied. Accordingly, immediately after terminating the former half of the second reset stage R2, all the display cell PCs are placed in a state that wall charges are formed negative nearby the row electrode Y and positive nearby the column electrode D.
In the latter half of the second reset stage R2 of the sub-field SF2, the Y-electrode driver 53 applies a negative reset pulse RP2Y2 that is moderate in potential transition at the leading edge with respect to the passage of time, to the row electrodes Y1-Yn. Furthermore, in the latter half of the second reset stage R2, the X-electrode driver 51 applies a positive base pulse BP+ having a predetermined base potential to the row electrodes X1-Xn. In response to the application of the negative reset pulse RP2Y2 and positive base pulse BP+, second reset discharge is caused between the row electrodes X and Y in all the display cells PCs. The reset pulse RP2Y2 and the base pulse BP+ each have a peak potential given minimally to cause second reset discharge positively between the row electrodes X and Y in consideration of the wall charges to be formed nearby the row electrodes X and Y in response to the first reset discharge. The reset pulse RP2Y2 is set with a negative peak potential higher in value than the peak potential of the negative write scanning pulse SPw, i.e. at a voltage approximate to 0 volt. Namely, this is because, if providing the peak potential of the reset pulse RP2Y2 lower than the peak potential of the write scanning pulse SPw, strong discharge results between the row electrode Y and the column electrode D to thereby greatly erase the wall charges formed nearby the column electrode D and hence make unstable the address discharge in the second selective write-address stage W2w. By the second reset discharge caused in the latter half of the second reset stage R2, erased are the wall charges that have been formed nearby the row electrodes X, Y in each of the display cells PCs thus initializing all the display cells PCs in the OFF mode. Furthermore, in response to the application of the reset pulse RP2Y2, weak discharge is caused between the row electrode Y and the column electrode D in all the display cells PCs. Due to the discharge, the positive wall charges formed nearby the column electrode D are partly erased away and adjusted into the amount that selective write-address discharge is to be caused correctly in the second selective write-address stage W2w.
In the second selective write-address stage W2w of the sub-field SF2, the Y-electrode driver 53 applies a write scanning pulse SPw having a negative peak potential selectively, in order, to the row electrode Y1-Yn while simultaneously applying to the row electrodes Y1-Yn a negative base pulse BP− having a predetermined base potential as shown in
In the sustain stage I of the sub-field SF2, the Y-electrode driver 53 generates a sustain pulse IP having positive peak potential in an amount of one pulse and applies it simultaneously to the row electrodes Y1-Yn. In this duration, the X-electrode driver 51 sets the row electrodes X1-Xn at a ground potential (0 volt) while the address driver 55 sets the column electrodes D1-Dm at a ground potential (0 volt). In response to the application of the sustain pulse IP, sustain discharge is caused between the row electrodes X and Y in the display cell PC being set in the ON mode. Due to the sustain discharge, the phosphor layer 17 gives off light toward the outside through the front transparent substrate 10, thus effecting once emission of display light correspondingly to the weight of luminance for the sub-field SF2. In response to the application of the sustain pulse IP, discharge is also caused between the row electrode Y and the column electrode D in the display cell PC being set in the ON mode. By such discharge together with the sustain discharge, negative wall charges are formed nearby the row electrode Y in the display cell PC while positive wall charges are formed nearby the row electrode X and the column electrode D. After the application of the sustain pulse IP, the Y-electrode driver 53 applies to the row electrodes Y1-Yn a wall-charge adjust pulse CP moderate in potential transition at the leading edge with respect to the passage of time and having a negative peak potential, as shown in
In the selective erase-address stage W0 in each of the sub-fields SF3-SF14, the Y-electrode driver 53 applies an erase scanning pulse SPD having a negative peak potential as shown in
When supplied with pixel-drive data bit having a logic level 0 for maintaining the display cell PC in its current status, it is converted into a pixel-data pulse DP having a low voltage (0 volt). The address driver 55 applies the pixel-data pulse DP in an amount of one display line (m in the number) per time to the column electrodes D1-Dm synchronously with the application timing of the erase scanning pulse SPD. On this occasion, selective erase-address discharge is caused between the column electrode D and the row electrode Y in the display cell PC to which the high-voltage pixel-data pulse DP is applied simultaneously with the erase scanning pulse SPD. By the selective erase-address discharge, the relevant display cell PC is set in a state that positive wall charges are formed nearby the row electrodes Y and X while negative wall charges are nearby the column electrode D, i.e. in the OFF mode. Such selective erase-address discharge is not caused between the column electrode D and the row electrode Y in the display cell PC to which a low-voltage (0 volt) pixel data pulse DP is applied simultaneously with the erase scanning pulse SPD. Accordingly, the relevant display cell PC remains in its state (in the ON mode or in the OFF mode).
In the sustain stage I of each of the sub-fields SF3-SF14, the X-electrode and Y-electrode drivers 51, 53 alternately apply sustain pulses IP having a positive peak potential respectively to the row electrodes X1-Xn and Y1-Yn, repeatedly in the (even) number of times corresponding to the weighting of luminance for the relevant sub-field, as shown in
After terminating the sustain stage I of the last sub-field SF14, the erase stage E is executed. In the erase stage E, the Y-electrode driver 53 applies an erase scanning pulse SPD′ having a negative peak potential as shown in
In the erase stage E, in order to place all the display cells PCs into the OFF mode, the address driver 55 applies address pulses DP, as erase pulses, in an amount of one display line (m in the number) per time to the column electrodes D1-Dm synchronously with the application timing of the erase scanning pulses SPD′ similarly to the case supplied with the pixel-drive data bit having a logic level 1. On this occasion, erase discharge is caused between the column electrode D and the row electrode Y in the display cell PC to which the address pulse DP′ is applied simultaneously with the erase scanning pulse SPD and staying in the ON mode. By the erase discharge, the display cells PCs staying in the ON mode are set in a state that wall charges are formed positive nearby the row electrodes Y and X and negative nearby the column electrode D, i.e. in the OFF mode. For the display cells PCs placed in the OFF mode at or before the sub-field SF13, the OFF mode is maintained. This places all the display cells PCs in the OFF mode.
The above driving is implemented based on 16 patterns of pixel drive data GD as shown in
At first, in the second gradation at which luminance is to be represented one level higher than the first gradation to exhibit black display (luminance level 0), selective write-address discharge is caused for setting the display cell PC in the ON mode, only in SF1 out of the sub-fields SF1-SF14 as shown in
In the third gradation at which luminance is to be represented one level higher than the second gradation, selective erase-address discharge is caused (shown with a double circle) for setting the display cell PC in the ON mode, only in SF2 out of the sub-fields SF1-SF14, followed by causing a selective erase-address discharge to transit the display cell PC into the OFF mode in the next sub-field SF3 (shown with a black circle). Accordingly, in the third gradation, light emission is effected based on once sustain discharge only in the sustain stage I of SF2 out of the sub-fields SF1-SF14, thus representing a luminance corresponding to the luminance level “1”.
In the fourth gradation at which luminance is to be represented one level higher than the third gradation, selective write-address discharge is first caused for setting the display cell PC in the ON mode in the sub-field SF1, thus causing the display cell PC set in the ON mode to discharge with slight emission (shown at a square). Furthermore, in the fourth gradation, selective write-address discharge is caused (shown at a double circle) for setting the display cell PC in the ON mode only in SF2 out of the sub-fields SF1-SF14, followed by causing a selective erase-address discharge to transit the display cell PC into the OFF mode in the next sub-field SF3 (shown with a black circle). Accordingly, in the fourth gradation, light emission is effected at a luminance level “α” in the sub-field SF1 and sustain discharge is once effected with light emission at a luminance level “1” in SF2, thus representing a luminance corresponding to the luminance level “α”+“1”.
In each of the fifth to sixteenth gradations, selective write-address discharge is caused for setting the display cell PC in the ON mode in the sub-field SF1, to cause a discharge with slight emission in the display cell PC being set in the ON mode (shown with a square). Then, selective erase-address discharge is caused to transit the display cell PC into the OFF mode, only in one sub-field corresponding to the luminance level (shown with a black circle). Accordingly, in each of the fifth to sixteenth gradations, slight-emission discharge is caused in the sub-field SF1. After causing once sustain discharge in SF2, sustain discharge is caused in the number of times assigned to the sub-field, in the sub-fields successive in the number (shown with white circles) corresponding to the relevant luminance level. Due to this, in each of the fifth to sixteenth gradations, visual perception is at a luminance correspondingly to the level of “α”+“total number of sustain discharges caused within the one-field (one-frame) display period”.
Namely, with the driving as shown in
In such driving scheme, there is no possibility that emission-pattern inverted regions (ON and OFF) coexist on one display screen in the one-field display period, which prevents a false contour from occurring in such a situation.
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
In the driving scheme shown in
In the embodiment shown in
Further, in the reset stage R shown in
In the foregoing embodiments, the scanning pulse SPD′, which is applied in the erase stage E, is line-sequentially applied for each scanning line, thereby sequentially effect erasure on a scanning-line-by-scanning-line basis. In the invention, the scanning pulse SPD′ may be applied for each scanning line group which is formed by a plurality of scanning lines as shown in
Furthermore, in the foregoing embodiments, the address pulse DP′ is applied to all the column electrodes D1-Dm regardless of whether each display cell PC is set in the ON mode or OFF mode at the time of terminating the sustain stage I of the sub-field SF14. Alternatively, the address pulse DP′ may be applied only to the display cells being set in the ON mode at the time terminating the sustain stage I of the sub-field SF14. Namely, even unless applying the address pulse DP′ to the display cells already set in the OFF mode in advance of the sub-field SF13, it is already in the OFF mode at the time of terminating the sustain stage I of the sub-field SF14. Accordingly, the structure may be to apply an address pulse DP′ only to the display cells being set in the ON mode in the sub-field SF14, according to the instruction from the drive control circuit 56. This reduces the number of times of address pulse DP′ applications and hence the power consumption as compared to the foregoing embodiment.
Incidentally, in
In
For example, the row electrodes Y1-Yn may be set at a ground potential in the former half of the reset stage R1, as shown in
The cathode-at-column discharge, of from the row electrode Y to the column electrode D in the former half of the reset stage R1, mainly aims at emitting priming particles in order to stabilize the write discharge in the first selective write-address stage W1w. However, when using a structure that a phosphor layer contains therein MgO crystallization containing a CL-emission MgO crystallization, e.g. in
In the case where write discharge stabilizes in the first selective write-address stage W1w wherein write discharge stabilizes in the first selective write-address stage W1w even unless causing a cathode-at-column discharge in the former half of the reset stage R1, a structure not to cause a discharge can be employed by setting both the row electrodes Y and the column electrodes D at a ground potential. In this case, the row electrodes X are also set with a ground potential as shown in
Incidentally, in this case, after terminating the reset stage R1, all the display cells are placed in a non-emission state by the discharge in the erasure stage of the preceding field and the discharge caused by the application of the pulse RP1Y2.
As for the cathode-at-column discharge caused by the application of the pulse RP2Y1 in the former half of the reset stage R2 in
This application is based on Japanese Patent Application No. 2007-038469 which is hereby incorporated by reference.
Number | Date | Country | Kind |
---|---|---|---|
2007-038469 | Feb 2007 | JP | national |