Claims
- 1. A thermal ink jet drop ejector, for ejecting an ink drop, generating thermal energy in response to an operating condition pulse, having a operating condition pulsewidth, being applied thereto during normal operation of the drop ejector, comprising:
- a silicon substrate;
- a field oxide layer, deposited on said silicon substrate;
- a polysilicon resistor, formed on said field oxide layer, said polysilicon resistor including a doped polysilicon material having a resistance value, the resistance value determined by adjustment with the application of a current pulse, generated by a signal generator, applied thereto, the current pulse, including a pulsewidth being equal to or greater than the operating condition pulsewidth, being applied repeatedly to said polysilicon resistor; and
- an insulator layer deposited on said polysilicon resistor.
- 2. The thermal ink jet drop ejector of claim 1, wherein said polysilicon resistor includes a polysilicon material having a resistance value being determined by adjustment with the creation of a temperature above approximately 400.degree. C. therein with the current pulse generated by the signal generator.
- 3. The thermal ink jet drop ejector of claim 2, wherein said insulator layer comprises a silicon nitride layer deposited on said polysilicon resistor and a cavitation layer formed on said silicon nitride layer.
- 4. The thermal ink jet drop ejector of claim 3, wherein said silicon nitride layer comprises a pyrolitically deposited silicon nitride.
- 5. The thermal ink jet drop ejector of claim 4, wherein said cavitation layer comprises tantalum.
- 6. The thermal ink jet drop ejector of claim 1, wherein said polysilicon resistor comprises a doped polysilicon material having the resistance determined by the current pulse being applied repeatedly to said polysilicon resistor for a total time period of one second or less.
Parent Case Info
This application is a continuation of Application Ser. No. 08/359,174, filed Dec. 19, 1994, now abandoned.
US Referenced Citations (8)
Non-Patent Literature Citations (1)
Entry |
Yoshihito Ameniya et al., "Electrical Trimming of Heavily Doped Polycrystalline Silicon Resistors", 1979, pp. 1738-1742, IEEE Transactions on Electron Devices, vol. ED-26, No. 11, Nov. 1979. |
Continuations (1)
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Number |
Date |
Country |
Parent |
359174 |
Dec 1994 |
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