Claims
- 1. A method for determining in software the effective address of instructions in a program executed on a pipelined architecture where there is no external visibility into the pipeline, the method comprising the steps of:
executing a first program; determining that a first instruction is in the pipeline; calculating the current effective address delay of the instruction in the pipeline; finding that a valid effective address for the instruction is available based on the current effective address delay of the instruction; computing the effective address of the instruction if a valid effective address is not available; and reporting the effective address of the instruction.
- 2. The method of claim 1 wherein:
the step of calculating comprises subtracting the number of clock cycles that have occurred since the instruction entered the pipeline from the number of clock cycles required to compute the effective address of the instruction; the step of finding comprises determining that the current effective address delay is 0; and the step of computing is executed if the current effective address delay is less than 0.
Priority Claims (1)
Number |
Date |
Country |
Kind |
01401752.9 |
Jun 2001 |
EP |
|
Parent Case Info
[0001] This application is related to and claims priority under 35 USC §119 (a) to European Application No. 01401752.9, (TI-32964EU) Method for Enhancing the Visibility of Effective Address Computation in Pipelined Architectures, filed on Jun. 29, 2001.