Patent Application
20080204068
The invention relates to defect testing of semiconductor integrated circuits (ICs) and, more particularly, relates to an IC test method by which defects causing current leakage during IC testing are better qualified and accounted for though the use of leveraging test data derived from prior testing of similar ICs.
Presently evolving semiconductor integrated circuit techmology is achieving higher levels of integration so that tens of thousands of circuits are being fabricated on a single semiconductor chip. Because of the high-density packing, the presence of micro-defects such as precipitates, dislocations, stacking faults, etc., are known to influence yield, performance and reliability of the semiconductor device. In particular, the aforementioned defects are known to cause what are known as “pipes,” or pipe defects, the presence of which may cause shorts or unwanted conductive paths between emitter and collector, lower voltage breakdowns, soft junctions, non-uniform doping, resistivity variations, etc. Transistor parameters such as gain, leakage current and saturation voltage are influenced by the numbers of pipe defects. In NPN transistors, pipe defects appear as N-type regions extending from the N emitter region, reaching the N collector region through the p-type base region. Such pipe defects result in a leakage current Ic when the device should be turned OFF. A more detailed description of pipe defects in semiconductor fabrication, and fabrication techniques for minimizing such defects may be found in U.S. Pat. No. 4,069,068, and U.S. Pat. No. 4,110,125, both commonly owned.
At IBM, semiconductor professionals are known to monitor leakage current in heterojunction bipolar transistor production, particularly in parallel-chain NPN devices for use in integrated circuit testing, One technique (“light-up” technique) includes destructive testing, wherein wafer areas under test are illuminated and the number and location of the defects may be estimated by photon emission associated with the defect when the transistors are biased in the sub-threshold region. That is, where the light generates a leakage current through a pipe defect, a thermal camera picks up the effect of the leaked current. The known light-up technique, however, is limited due to its destructive nature, and the limited data acquired.
Detection of one defect in one transistor within a chain of 1000 transistors, or 10,000 transistors should not require that the semiconductor IC be discarded. A single defect may be caused by quite another problem than a case where 30 or 100 defects are found in a similarly sized chain (and IC). Conventional non-destructive techniques for production testing, however, merely qualify testing results as simply pass/fail. They are not known distinguish an IC with one transistor fail from an IC with 30 or 100 transistor fails. In particular, NPN devices are “failed” using conventional non-destructive testing techniques where currents detected are overly high. But little specific information is obtained about the actual number of defects relating to overly high detected current using conventional testing techniques. By better characterizing defects, e.g., pipe defects, and their numbers within an IC under production testing, test procedure utility may be extended to better qualify failures. By better qualifying failures, the IC may be better qualified such that some wafers may be used for some purposes rather than merely discarded, as the case using conventional related testing.
The present invention provides an improved method for testing and characterizing defects in NPN BJTs and HBTs based on a linear relationship derived from prior testing of similarly manufactured integrated circuits having a known number of defects. The prior testing qualifies the number of known defects and the sub-threshold collector currents in the known BJTs and HBTs, and deriving the linear relationship therefrom. The novel testing method requires grounding the emitter and fixing the collector and base potential in the sub threshold region to obtain the conductance or resistance of the NPN device under production test. Potentials at the sub threshold regions are well below those potentials that tend to precipitate an onset of avalanching. Through use of the known linear relation, known number of defects and the acquired resistance/conductance of the similar IC under test results, defects in the IC under test may be relatively accurately estimated and characterized. That is, by knowing resistances at particular testing potentials in an IC under test, the number of defects in the IC may be reliably projected using the known linear relation derived from the known prior tested IC and the linear relation derived by said prior testing. The defect projection data derived by the inventive method allows for a more detailed understanding of the inherent nature of the IC under test (production IC). A more detailed understanding of the IC under test may allow that ICs that would be normally discarded in view of conventional test results may be used nevertheless for particular applications.
In one embodiment, the invention comprises a method for testing bipolar transistors in an integrated circuit (IC) using a known linear relation derived from test measurement data from prior testing of similar bipolar transistors. By use of the linear relation, and a detected current in the IC under test, a number of defects may be accurately estimated to qualify the defects in the IC under test. The method includes measuring a first conductance of a leakage path between a collector and emitter of a first plurality of bipolar transistors having a known number of defects, and calculating a per defect conductance value and deriving the linear relation. With the linear relation, the method then measures a second conductance of a leakage path between a collector and emitter of a second plurality of bipolar transistors under test, having an unknown number of defects. The second conductances and the linear relation provides for determining substantially the number of defects related to the second plurality and characterizing those defects and the IC thereby.
a, 1b, 1c and 1d are a collection of I-V plots or characteristic curves of one or more transistors taken under test to illustrate the fundamental biasing, testing and defect qualification of the invention herein; and
The inventive method includes the use of a known linear relation of defect conductance values derived from testing a first IC (with known defects) to determine or estimate a number of defects in a second IC under production testing (with an unknown number of defects) by using the result testing conductance paths between collector and emitter in the second IC. For example, the first number of transistors may comprise a chain of 2000, or 20,000 transistors, or a plurality of such chains built into a semiconductor wafer or IC. Destructively testing the first number of transistors may be required to acquire the resistance or conduction path data, and the number of defected transistors, to calculate the linear relationship of the per defect conductance. By knowing the linear relation between numbers of defects, e.g., pipe defect density, the number and severity of defects may be accurately estimated in production ICs under test by determining the conductance or leakage current during the production testing. That is, using the known data and linear relation, defects may be estimated by measuring the production IC's base to emitter currents and using the known linear relation to estimate the severity and/or number of defects in the production IC under test. Accurately estimating or determining the number and character of defects in the production IC provides for an understanding of the impact, or lack of impact, the defects could have on a customer design.
To better understand the invention, the reader's attention is directed to a set of four (4) figures depicting current voltage (I-V) characteristic curves from testing in accord with the inventive method. That is,
As mentioned, the emitter(s) is/are grounded during the testing, and the collectors swept from 0 to 1.5 V, which is below BVCEO of 2 V for this specific device type. The reader should note that BVCEO varies with device type so that BVCEO is chosen for a specific device type. Concurrently, the base is swept from −0.5 V to +0.9 V. The
From the slope of these I-V curves (
Although a few examples of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.
