Method for fabricating a compound-material and method for choosing a wafer

Abstract

The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be understood more fully by reference to the following detailed description of the preferred embodiment of the present invention, illustrative examples of specific embodiments of the invention and the appended figures in which:

FIGS. 1 a-e illustrate a fabrication process of compound-material wafers;

FIGS. 2 a-b illustrate a compound-material wafer with defects close to the outer periphery in a top view and in a crosscut view;

FIG. 3 illustrates a block diagram of an embodiment of the inventive method for fabricating a compound-material wafer;

FIG. 4 illustrates a method for determining the edge roll off value using the second derivative; and

FIG. 5 illustrates a three-dimensional diagram representing the average number of void defects as a function of the ERO value of two wafers that are used in the fabrication process of a compound-material wafer according to this invention;

Claims

1. A method for fabricating a compound-material wafer from two or more initial wafers comprising: determining a second derivative of the profile of the wafers,determining an edge roll off (ERO) value of the wafers in dependence on the determined second derivative,selecting two wafers having ERO values of more than approximately 50 nm, andattaching the two selected wafers together.

2. The method of claim 1, wherein the selected wafers have ERO values of more than approximately 100 to 150 nm.

3. The method of claim 1, wherein the compound-material wafer comprises a silicon-on-insulator (SOI) type wafer.

4. The method of claim 1, wherein the attaching comprises bonding.

5. The method of claim 4, wherein the bonding is molecular bonding.

6. The method of claim 1 wherein at least one ERO value is determined according to the equation: ERO=Y(a)−Y(fqa),

7. The method of claim 6, wherein “fga” is selected to be a radial position of approximately 1 mm away from the outer periphery of the wafer.

8. The method of claim 1, wherein each of the wafers is a 300 mm type wafer.

9. The method of claim 1, wherein determining an ERO value further comprises: determining candidate ERO values at a plurality of positions on the wafer, anddetermining the ERO value by averaging the candidate ERO values.

10. The method of claim 1, which further comprises providing an insulating layer on at least one of the selected wafers prior to attaching the wafers.

11. The method of claim 10, which further comprises forming a predetermined splitting area in one of the selected wafers.

12. A method for selecting a wafer suitable for use in fabricating a compound-material wafer comprising: determining an edge roll off (ERO) value of the wafer, andselecting the wafer if the ERO value of the wafer is more than approximately 50 nm.

13. The method of claim 12, wherein the wafer is selected if the ERO value of the wafer is more than approximately 100 to 150 nm.

14. The method of claim 12, wherein the compound-material wafer to be fabricated is a silicon-on-insulator type wafer.

15. The method of claim 12 which further comprises fabricating a compound-material wafer from the selected wafer.

16. The method of claim 12 which further comprises determining a second derivative of the profile of the wafer, wherein the ERO value is determined dependence on the determined second derivative,

17. The method of claim 12, wherein the ERO value is determined according to the equation: ERO=Y(a)−Y(fqa),

18. The method of claim 17, wherein “fga” is selected to be a radial position of approximately 1 mm away from the outer periphery of the wafer.

18. The method of claim 12, wherein determining an ERO value further comprises: determining candidate ERO values at a plurality of positions on the wafer, anddetermining the ERO value by averaging the candidate ERO values.

20. The method of claim 12, wherein the wafer is a 300 nm type wafer.