Method for fabricating a transistor device with a tuned dopant profile

Abstract

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.

Description

TECHNICAL FIELD

The present disclosure relates in general to semiconductor fabrication processes and more particularly to a method for fabricating a transistor device with a tuned dopant profile.

BACKGROUND

Cost effective semiconductor electronic manufacturing requires transistor structures and manufacturing processes that are reliable at nanometer scales and that do not require expensive or unavailable tools or process control conditions for the design or manufacture. While it is difficult to balance the many variables that control transistor electrical performance, finding suitable transistor dopant structures with an associated manufacturing technique that results in acceptable electrical characteristics such as charge carrier mobility, threshold voltage levels, and junction leakage are a key aspect of such commercially useful transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

FIGS. 1A-1C illustrate how a carbon implant may be used to adjust a dopant profile of a boron implant;

FIGS. 2A-2B illustrate examples of how a position and height of a peak of the dopant profile can be adjusted through a change in the carbon implant;

FIGS. 3A-3F illustrate changes in a transistor structure during a fabrication process to produce the dopant profiles of FIGS. 1A-1C and 2A-2B;

FIG. 4 illustrates an example of a transistor structure without a screening layer, with carbon added to the channel.

DETAILED DESCRIPTION

A Deeply Depleted Channel (DDC) transistor can use, among other things, dopants in preselected concentrations and located specific areas a distance below the top surface of the substrate to define a depletion zone and establish a threshold voltage during transistor operation. This can result in a transistor having improved electrical parameters including threshold voltage variation among transistors and reduced power requirements. One quality goal of a DDC transistor is to form the doped regions in such a manner as to inhibit the migration of the dopants outside of the desired locations.

A DDC transistor typically includes both a highly doped region formed in a semiconductor substrate below a gate, called the screening layer, that functions to define the extent of the depletion region below the gate in operation, and an undoped epitaxially grown channel on the highly doped region extending between a source and a drain of the transistor. In addition, a threshold voltage set layer may be positioned between the undoped channel and the screening layer and may alternatively contact or be separated from the screening layer and/or the undoped channel. This threshold voltage set layer is used to finely adjust or tune the threshold voltage of individual or blocks of transistors. The screening layer and/or the threshold voltage set layer can be implanted into the semiconductor substrate, separately grown as a blanket or as selective epitaxial layers on the semiconductor substrate and doped by controlled implants, or by substitutional doped deposition. The threshold voltage set layer may also be formed by performing a controlled diffusion from the screening layer. An anti-punchthrough layer may also underlie the screening layer and may be formed by implantation into the semiconductor substrate or by diffusion from the screening layer. As compared to conventional doped channel transistors, such DDC transistors can be more closely matched in device characteristics, in part because they have reduced channel random dopant fluctuations that can result in variable threshold voltage set points. Other embodiments of DDC transistors may include a slightly doped channel, whether by way of channel dopants distributed throughout or halo implants or other forms of channel doping. Further examples of a DDC transistor structure and manufacture are disclosed in U.S. Pat. No. 8,273,617 titled ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME by Scott E. Thompson et al., as well as U.S. patent application Ser. No. 12/971,884, filed on Dec. 17, 2010 titled LOW POWER SEMICONDUCTOR TRANSISTOR STRUCTURE AND METHOD OF FABRICATION THEREOF and U.S. patent application Ser. No. 12/971,955 filed on Dec. 17, 2010 titled TRANSISTOR WITH THRESHOLD VOLTAGE SET NOTCH AND METHOD OF FABRICATION THEREOF, the respective contents of which are incorporated by reference herein.

Thermal cycles in the fabrication process can lead to diffusion of the screening and threshold voltage set layer materials particularly when the materials used tend to be mobile. It is desirable to prevent screening layer and threshold voltage set layer materials from unwanted diffusion into the undoped channel layer. A method of reducing dopant migration is to introduce a dopant migration resistant material, such as carbon, to further limit unwanted dopant migration.

As an example, boron is preferably used for NMOS transistor fabrication. For a DDC NMOS transistor, a boron implant may be used for a screening layer and for the optional threshold voltage set layer. Implanted boron is widely known to diffuse during device fabrication, especially in thermal cycles of 900° C. or more. To avoid unwanted diffusion of boron, carbon may be added to the crystalline lattice. It is thought that carbon takes substitutional positions in the crystalline structure to limit available pathways for the movement of boron. There may be a pre-amorphization implant using germanium followed by a recrystallization anneal to enhance the effectiveness of the added carbon. The use of carbon addition to inhibit migration of dopants works effectively in a silicon crystalline substrate, and can be effective in other semiconducting substrates as well. Another benefit to using carbon implant is in its ability to tune the dopant profile of the boron.

FIGS. 1A-1C show by way of example how a carbon implant may be used to adjust a dopant profile of a boron used for a screening layer or a threshold voltage set layer of the DDC transistor. Throughout FIGS. 1A-1C, the dose of the boron implant is constant at 3.5×10¹³ atoms/cm² to achieve a peak concentration as shown on the charts. In each of FIGS. 1A-1C, two dopant profiles are shown, one at a BF2 implant energy of 5 keV and one at an implant energy of 20 keV. Though results are shown for BF2, the effects shown herein apply to a boron implant as well. FIG. 1A shows the effect of a carbon implant at an implant energy of 3 keV and an implant dose of 5×10¹⁴ atoms/cm² on the boron dopant profile. FIG. 1B shows the effect of a carbon implant at an implant energy of 1 keV and an implant dose of 5×10¹⁴ atoms/cm² on the boron dopant profile. FIG. 1C shows the effect of a carbon implant at an implant energy of 3 keV and an implant dose of 8×10¹⁴ atoms/cm² on the boron dopant profile.

As shown in FIGS. 1A-1C, the amount of implant energy for the carbon implant has a visible effect on the resultant boron dopant profile. For instance, as seen in FIG. 1B, a lower carbon implant energy, for instance, 1 keV, produces a sharper and higher peak in the boron dopant profile than for a carbon implant energy of 3 keV, where, as seen in FIGS. 1A and 1C, the boron dopant profile is more spread out. Moreover, boron dopant profile peak height and location may also be changed even when the carbon implant remains constant and the BF2 implant energy is adjusted. Another characteristic illustrated by FIGS. 1A-1C is that a tail of the dopant profile is affected by an amount of implant energy for the BF2 implant. Degradation of the dopant profile tail at lower implant energies for the BF2 implant may lead to higher drain induced barrier lowering (DIEL), greater short channel effects, and less threshold voltage response.

FIGS. 2A-2B show examples of how a position and height of a peak of the boron dopant, profile can be adjusted through a change in the carbon implant. The example of FIG. 2A uses BF2 as the dopant material implanted at an energy of 5 keV and a dopant implant dose of 3.5×10¹³ atoms/cm². The peak of the boron dopant profile is sharper and higher and occurs at a shallower depth for a carbon implant energy of 1 keV as compared to keV. As a result, fine tuning of the boron dopant profile is achieved through variations in carbon implant parameters, with the carbon energy being tied to the sharpness of the peak for the boron profile. A lower carbon energy is used to attain a sharper boron peak. A lower carbon energy also causes the peak of the boron to be shallower and higher in concentration than for a higher carbon energy. Changes in carbon implant dose has a negligible effect on the boron dopant profile in this example, with very slight increases in peak height and sharpness of the dopant profile occurring at increased doses of the carbon implant. As a result, the boron dopant profile is more affected by carbon implant energy than carbon dopant concentration. However, increased carbon dopant concentration may protect the screening layer and the threshold voltage set layer from encroachment of subsequently formed lightly doped drain or source/drain extension regions.

The example of FIG. 2B uses BF2 as the dopant material implanted at an energy of 20 keV and a dopant implant dose of 3.5×10¹³ atoms/cm². Similar changes in location and height of the peak of the dopant profile are achieved relative to carbon implant energy as similarly shown in FIG. 2A. Note that, as indicated in FIG. 2A-2B, a dual implant of carbon can be used to attain a dual peak profile for the boron. A lower-energy carbon, for instance, at an energy of about 1 keV, can be combined with a higher energy carbon, for instance, at an energy of about 3 keV, to produce a dual peak profile for the boron of a first, sharper, shallower peak and a second, wider, deeper peak. Finer dopant profile tuning can be made with modifications to the carbon dose.

FIGS. 3A-3F show an example of the changes that may take place in a transistor channel structure 300 during a fabrication process to produce the dopant profiles of FIGS. 1A-1C and 2A-2B. The process begins in FIG. 3A with a mask 302 formed on a semiconductor substrate 304 (preferably bulk silicon) to define an opening constituting an implant region 306. In one embodiment for an NMOS transistor device, a p-type material (for discussion purposes Boron or BF2) is implanted in the opening 306, at approximately 100-250 keV at doses in the range of 1×10¹³ to 5×10¹³ atoms/cm², to form a well 308.

In FIG. 3B, an optional anti-punchthrough layer 310 comprising a p-type material may be implanted into opening 306. An example implant condition for anti-punchthrough layer 310 may include an implant energy of 30 to 50 keV and a dopant concentration of about 0.8 to 3.0×10¹³ atoms/cm².

In FIG. 3C, dopant migration resistant material such as carbon is implanted into opening 306. An example process condition may include a germanium implant at an implant energy of 30 to 50 keV and a dopant implant dose of 4 to 6×10¹⁴ atoms/cm². Multiple carbon implants may be performed for further dopant profile tuning as desired. For instance, each carbon implant can correspond respectively to one or more of anti-punchthrough layer 310 and a subsequently formed screening layer and a subsequently formed threshold voltage set layer. The process conditions for the carbon implants may include those discussed above, with energy selections tailored to tune the dopant profile of the anti-punchthrough layer 310, the screening layer, the threshold voltage set layer and any other desired profiles. The carbon implant may be performed once for all dopant profile tunings, or may be performed in steps specifically matched to steps for one or more of the dopant regions. Notably, the dopant profile shape for one or more screening layers and if present, the threshold voltage set layer are designed for the transistor to meet its parametric requirements. Therefore, implementing a process that matches an appropriate carbon implant energy to targeted dopant profile shapes is beneficial for achieving structural and device metric goals for the transistor. Example carbon implant conditions may include an implant energy of 0.8 to 8 keV and a dopant implant dose of 3×10¹³ to 8×10¹⁴ atoms/cm². A particularly shallow carbon implant may serve an additional benefit to contain the profile of the to-be-formed source/drain extensions (shown as 322, 324 in FIG. 3F). A deeper carbon implant may be used to control the shape of a more deeply implanted dopant, for example anti-punchthrough layer 310. The carbon implant conditions are selected to place a peak of the dopant profile of the anti-punchthrough layer 310, the screening layer, and the threshold voltage set layer at a desired location and height.

After the germanium and carbon implants, transistor structure 300 is usually subjected to one or more annealing processes. Example annealing processes include baking transistor structure 300 at a temperature of 600 to 700° C. for 80 to 200 seconds. A spike anneal may also be performed at an example temperature of 900 to 1100° C. for a duration of less than 1 second. The anneal processes are selected and performed to recrystallize the semiconductor substrate while suppressing diffusion of implanted dopants.

In FIG. 3D, a screening layer 312 and a threshold voltage set layer 314 are implanted into implant region 306. In an alternative process, anti-punchthrough layer 310 may also be implanted at this time instead of prior to the germanium implant as stated above. Example implant conditions include those discussed above where screening layer 312 may be implanted with a p-type material at an implant energy of 10 to 30 keV and a dopant implant dose of 2 to 5×10¹³ atoms/cm². Threshold voltage set layer 314 may be implanted with a p-type material at an implant energy of 3 to 20 keV and a dopant implant dose of 1 to 4×10¹³ atoms/cm². In alternative embodiments, screening layer 312 may have a higher dopant concentration, approximately the same, or lower dopant concentration than that of threshold voltage set layer 314 so that the screening layer 312 may be below or above the threshold voltage set layer 314. The desired peak sharpness of the screening layer 312 and threshold voltage set layer 314 are modulated by setting the carbon implant energy that matches the desired outcome, that is a lower carbon implant energy resulting in sharper, higher peaks with a more narrow profile. Typically, the dopant concentration of the anti-punchthrough layer 310 is lower than both the screening layer 312 and threshold voltage set layer 314. Implantation of screening layer 312 and threshold voltage set layer 314 may be performed in separate implant steps or as a single continuous step through dynamic adjustment of the process conditions.

In FIG. 3E, following screening layer 312 and threshold voltage set layer 314 implantation, transistor structure 300 may be subject to one or more anneal processes as discussed above in order to further prevent diffusion of the dopants in these layers. Mask 302 is removed and a blanket undoped channel layer 316 may then be epitaxially grown across a plurality of transistor structures 300 on a single die (not shown).

In FIG. 3F, a gate dielectric 322, a gate region 324, and sidewall spacers 326 may be formed over undoped channel 316. Note that although a planar CMOS structure is depicted in the FIGURE, alternative transistor structures above the channel 316 may be formed. An n-type material may be implanted to form a source extension 322 and drain extension 324 as well as a source region 318 and a drain region 320.

The above embodiments for using a diffusion-mitigating material in the context of DDC transistors is applicable for both NMOS and PMOS transistors, though typically, such methods may be used more commonly for NMOS and less commonly for PMOS. For PMOS, other materials which in themselves tend to be less diffusive may be used. For instance, antimony may be used for the highly doped regions of the PMOS transistor, thus making potentially unnecessary the use of further diffusion-mitigation measures. For PMOS, energy and dose levels for ion implantation of the dopant material (for instance, antimony) are selected to effect a targeted placement of the profile peak as well as thickness and concentration of the doped region, all of which can affect resultant electrical parameters for the transistor including threshold voltage, junction leakage, drive current, drain-induced barrier lowering, and other parameters. However, an alternative embodiment may be to deposit a blanket epitaxial carbon-infused silicon on the substrate surface in advance of or after the doping of the highly doped regions (for instance, the screen layer and the threshold voltage setting layer). Such a blanket epitaxial carbon-infused silicon may serve as an overall dopant migration inhibitor for all devices. Implanted dopant migration mitigation material (for instance, carbon) may be used to augment in-situ epitaxially grown material as needed. Adjacent transistor structures 300 may be separated by isolation regions 326, with the isolation regions being preferably formed after the epitaxial layer is formed. Further conventional process steps can then be performed to complete the fabrication to form an integrated circuit.

As a further note, as shown in FIG. 4, preselected carbon implants may be performed in the absence of a screening layer or threshold voltage tuning layer (not shown). There is provided a transistor 400 which contains, in this example, a gate 402 and spacer structures 404 on either side of gate 402 overlying a gate dielectric 406 which may be a thermally grown oxide or other suitable material. There may be source and drain extension structures 410 and 412 extending below and near the edges of gate 402 with spacers 404. There may be deeper source and drain structures 420 and 422, doped to a level sufficient to provide a suitable contact to metallization which may be formed thereabove (not shown).

There may not be an undoped epitaxially grown channel as preferably used for DDC transistor structures. Carbon addition 430 may be made by ion implantation directly into substrate 428 which may be previously doped with wells (not shown) or the wells may be formed after the carbon implants. Instead of implanted carbon, carbon addition 430 may be epitaxially introduced by way of an epitaxial material growth over substrate 428 that includes carbon, resulting in carbon addition 430 appearing in the channel. A benefit of using carbon-added epitaxially grown silicon is the avoidance of using germanium pre-amorphization implants. If instead, carbon is put into the substrate by way of ion implantation, then germanium pre-amorphization may be typically followed by recrystallization anneal to secure the carbon into the substitutional lattice locations. Germanium pre-amorphization implant may, however, be avoided with the selection of an appropriate ion implantation process for the carbon, for instance through use of low-temperature ion implantation methods.

Preselected carbon implants (the process shall be referred to herein as “implants” though in-situ epitaxially introduced carbon alone or in combination with ion implantation of carbon may be used) may be used in the context of a DDC transistor, with conventional channel doping implementations or halo doping implementations, or both. The carbon is introduced into substrate 428 so that the carbon concentration and, as applicable, the profile may be matched to those areas of the source 420, drain 422, source extension 410, and drain extension 412 tending to produce unwanted out-diffusion. Typically, carbon may be added to substrate 428 uniformly in the deep source 420/drain 422 area with the concentration being modulated at the source extension 410/drain extension 412 area to fine-tune the electrical parameters of the transistor device which may be affected by tolerance for more or less out-diffusion of material from the doped areas 410, 412, 420 and 422.

Preselected carbon implants may be used with the isolation structures formed first or right after placement of carbon addition 430, or sometime later in the fabrication process sequence. Preferably, the isolation structures are formed after the carbon implants.

Energy for implanting the carbon implants may range from 0.5 to 10 keV for a dose of 8×10¹³ to 2×10¹⁵ atoms/cm² or other dose to result in a sufficient concentration of carbon to effect a stop for potential diffusion of the later formed source 420, drain 422, source extension 410, and drain extension 412. Concentration of the carbon in the semiconductor lattice may be, for instance, 1×10¹⁸ atoms/cm³ to 8×10²⁰ atoms/cm³ where the concentrations may be more precisely located to be in the vicinity of the source extension 410/drain extension 412 or source 420/drain 422. The carbon concentration and location of concentration profile peaks can be tuned with the selection of energies and dose, as can be seen in the examples of FIGS. 1A TO 1C, and FIGS. 2A TO 2B. If a dual carbon profile is desired, the profile can be achieved using a combination of ion implant steps or using a combination of in-situ carbon epitaxial growth at a designated carbon concentration with separately performed ion implantation.

A benefit of using carbon implants in the channel is multi-fold. In the case of DDC transistors, carbon helps to mitigate against unwanted diffusion doped regions to effect a desired and specific dopant profile. In the case of conventional transistors, there is usually a greater problem of out-diffusion from the source and drain structures due to high temperature anneals that take place later in the process sequence. The high temperature anneals may cause excessive out-diffusion of material, for instance boron or phosphorous, from the source and drain structures. By introducing carbon into the channel prior to the initiation of the anneals that may cause excessive out-diffusion of the source and drain into the channel region, the otherwise occurring out-diffusion of material from the source and drain structures can be mitigated. Though the carbon implants may be formed at any time prior to the problematic anneals, the carbon implants are preferably formed together with, before, or right after the formation of the wells.

Note that although a well-known structure for a MOSFET is shown in FIG. 4, the embodiment of placing carbon into the channel is useful for a variety of MOSFET structures including structures having shallower junction, raised source and drain, source and/or drain structures created with selective epitaxial growth, having or not having source/drain extensions, or other variations thereof. Placing carbon in the channel is useful for either NMOS or PMOS, and carbon placement to tune dopant profile of adjacent doped structures can be used in non-MOSFET contexts as well, for instance in bipolar or other structures that involve doped regions that should remain in place. Carbon in the channel is useful for numerous types of DDC structures as described above in relation to FIGS. 1A to 1C, 2A to 2B, and 3A to 3F, as well as the previous cases incorporated by reference herein. Carbon in the channel may also be used in three-dimensional transistor structures, for instance finFET devices, where it is desired to block the out-diffusion of source/drain dopant material into a non-doped, lesser doped, or oppositely doped area.

Different process conditions for doping may be implemented across a plurality of transistors in a die. Through selective use of doping conditions across a plurality of transistors, transistor structures may be fabricated with variations in location and height of the peak of the dopant profile so as to effect differing electrical transistor behaviors. Doping conditions within the channel may directly affect certain electrical properties such as threshold voltage. Doping profile of other parts of the transistor, for instance the source and drain, should also be controlled, though out-diffusion that results in a modification of the shape of the source and drain can create problems with transistors not meeting parametric targets. The use of carbon or other dopant migration mitigation materials is effective to hold a dopant material that would otherwise travel through a semiconductor lattice in place to effect a dopant desired profile. More specifically, the use of preselected carbon process conditions to effect a placement of carbon into the substrate has beneficial effects on keeping the target shape for the doped areas. If ion implantation is used for introducing the carbon, the modulation of energy of the implant results in a certain shape of a dopant profile peak. To insert carbon into the substrate, ion implantation, in-situ epitaxial growth, or other methods or combinations thereof may be used to effect a placement of a concentration of carbon species in desired locations.

Although the present disclosure has been described in detail with reference to a particular embodiment, it should be understood that various other changes, substitutions, and alterations may be made hereto without departing from the spirit and scope of the appended claims. For example, although the present disclosure includes a description with reference to a specific ordering of processes, other process sequencing may be followed to achieve the end result discussed herein. Though discussed using specific examples, different materials and process conditions may be used at each point of the fabrication process to create a desired transistor structure. As but one example, the carbon implants may be intermixed with the various boron implants.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the spirit and scope of the appended claims. Moreover, the present disclosure is not intended to be limited in any way by any statement in the specification that is not otherwise reflected in the appended claims.

Claims

1. A method for fabricating a transistor device having a gate, a channel, a source and a drain on either side of the channel, the channel having a tuned dopant profile, comprising: defining an implant region;performing a first implantation of a first dopant migration mitigating material into the implant region at a first preselected dopant migration mitigating energy and dose;implanting a screening layer into the implant region at a preselected screening layer energy and screening layer dose, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;implanting a threshold voltage set layer into the implant region at a preselected threshold voltage set layer energy and threshold voltage set layer dose;wherein the first preselected dopant migration mitigating energy effects the placement of a peak of a dopant profile of the screening layer at a first location and a first thickness;wherein the preselected threshold voltage set layer energy and threshold voltage set layer dose effects the placement of the peak of a dopant profile of the threshold voltage layer to be different from the first location;wherein the threshold voltage set layer is coextensive with the screening layer and abuts the source and drain and the screening layer extends laterally across the channel.

2. The method of claim 1, further including the step of performing a second implantation of a second dopant mitigating material at a second preselected dopant mitigating material energy and dose.

3. The method of claim 2, wherein the first implantation of a dopant migration mitigating material is implanted at a first energy and the second implantation of a dopant migration mitigating material is implanted at a second energy, the first energy being lower than the second energy.

4. The method of claim 2, wherein both the first dopant migration mitigating material and second dopant migration mitigating material comprise carbon.

5. The method of claim 4, wherein the first implantation is at a first energy, and the second implantation is at a second energy, the second energy being higher than the first energy.

6. The method of claim 1, wherein the first and second energies for the first and second dopant migration mitigating material implantations are identical.

7. The method of claim 1, wherein the first dopant migration mitigating material comprises carbon.

8. The method of claim 1, further comprising: creating a narrower peak profile for the screening layer compared with the threshold voltage set layer.

9. The method of claim 1, further comprising: implanting an anti-punchthrough layer into the implant region.

10. The method of claim 1, further comprising: forming an undoped channel layer on the implant region.

11. A method for fabricating transistor devices with tuned dopant profiles, comprising: providing a first implant region for a first transistor device;performing a first implantation of a carbon material into the first implant region;performing a second implantation of a carbon material into the first implant region;implanting a first screening layer into the first implant region;providing a second implant region for a second transistor device;implanting a second screening layer into the second implant region;wherein process conditions for implanting the first implantation of a carbon material and the second implantation of a carbon material and the first screening layer are selected to effect a location of a peak and thickness of a dopant profile of the first screening layer;wherein process conditions for implanting a second screening layer are selected to effect a location of a peak and thickness of a dopant profile of the second screening layer.

12. The method of claim 11, further including the step of implanting a first threshold voltage layer into the first implant region.

13. The method of claim 11, further including the step of implanting a second threshold voltage layer into the second implant region.

14. The method of claim 11, further comprising: selecting a lower energy for the first implantation and a higher energy for the second implantation, resulting in a narrower peak profile for the first screening layer as a result of the selection of the lower energy for the first implantation.