Claims
- 1. A method for fabricating an isolation region in a semiconductor device formed with a semiconductor substrate having a U-shaped isolation groove, comprising:
- coating said isolation groove with a first insulating layer:
- filling the coated groove with polycrystalline semiconductor material at least to a first depth below the surface of said substrate; and
- depositing a second insulating layer on said polycrystalline semiconductor material so as to at least fill said isolation groove up to said substrate surface..]. .[.2. The method of claim 1, comprising, prior to depositing said second insulating layer:
- continuing said filling of said coated groove with said polycrystalline semiconductor material to fill said coated groove above said first depth; and
- etching said polycrystalline semiconductor material in said coated groove down to said first depth..]. .[.3. The method of claim 2, said filling of said coated groove with said polycrystalline semiconductor material also comprising depositing said polycrystalline semiconductor material on said substrate surface, said method comprising continuing said filling of said coated groove with said polycrystalline semiconductor material so as to bury said isolation groove, prior to said etching of said polycrystalline semiconductor material to said first depth..]. .[.4. The method of claim 2 or 3, said etching of said polycrystalline semiconductor material
- comprising a wet etching process..]. 5. The method of claim .[.1, 2 or 3, comprising forming.]. .Iadd.19, wherein .Iaddend.said .[.first.]. depth .Iadd.location is at a distance .Iaddend..[.to be.]. in the range of from 0.2 to 1.0 micron .[.from.]. .Iadd.below the exposed upper surface of
- .Iaddend.said substrate .[.surface.].. 6. The method of claim .[.1, 2 or 3.]. .Iadd.19, .Iaddend.comprising providing said substrate to be of silicon, each said insulating layer to be of silicon dioxide, and said
- polycrystalline semiconductor material to be of silicon. .[.7. The method of claim 1, 2 or 3, wherein the top surface of said second insulating layer provides said substrate surface with an effectively flat surface in the vicinity of the isolation region and the isolation region is provided with a width that is effectively the width of the isolation groove..]. .[.8. The method of claim 1, 2 or 3, said depositing of said second insulating layer including coating the surface of said substrate with said second insulating layer, said method further comprising:
- continuing said depositing of said second insulating layer so as to bury said coated groove; and
- removing said second insulating layer on said substrate surface and from above said substrate surface over said isolation groove..]. .[.9. The method of claim 8, comprising providing said substrate to be of silicon, each said insulating layer to be of silicon dioxide, and said polycrystalline semiconductor material to be of silicon..]. .[.10. The method of claim 8, said removing of said second insulating layer comprising at least one of etching and polishing..]. .[.11. The method of claim 8, wherein the top surface of said second insulating layer provides said substrate surface with an effectively flat surface in the vicinity of the isolation region and the isolation region is provided with a width that is effectively the width of the isolation groove..]. .[.12. The method of claim 8, comprising forming said first depth to be in the range
- from 0.2 to 1 micron from said substrate surface..]. 13. The method of claim .[.12, comprising providing.]. .Iadd.5, wherein .Iaddend.said .[.first.]. .Iadd.defined .Iaddend.depth .[.to be.]. .Iadd.is at a distance of .Iaddend.at least 0.5 .[.microns.]. .Iadd.micron below the
- exposed upper surface of said substrate.Iaddend.. 14. The method of claim .[.8, said method.]. .Iadd.19, further .Iaddend.comprising forming said substrate of a slice of single crystal semiconductor with at least one layer of doped semiconductor .[.as the top.]. .Iadd.on the major surface .Iaddend.of the slice and a semiconductor oxide layer .Iadd.superposed .Iaddend.on the .[.top.]. doped layer,
- forming said isolation groove being deeper than each said doped layer, and
- forming the thickness of said layer of semiconductor oxide to be smaller
- than said first depth. 15. The method of claim 14, comprising
- forming a layer of semiconductor nitride .Iadd.in superposed relationship .Iaddend.on said layer of semiconductor oxide, prior to .Iadd.forming .Iaddend.said coating of .[.said groove with.]. said first insulating layer .Iadd.on the sidewalls and the bottom wall of said groove, .Iaddend.and
- removing said layer of semiconductor nitride after said removing .Iadd.of a portion .Iaddend.of said second insulating layer. .[.16. The method of claim 15, comprising providing the thickness of said layer of silicon nitride to be smaller than said first depth..]. .[.17. The method of claim 15, wherein the top surface of said second insulating layer provides said substrate surface with an effectively flat surface in the vicinity of the isolation region abd the isolation region is provided with a width that is
- effectively the width of the isolation groove..]. 18. The method of claim 15, comprising providing said substrate and said polycrystalline semiconductor material to be of silicon, each said insulating layer and said layer of semiconductor oxide to be of silicon oxide (SiO.sub.2), and said semiconductor nitride to be of silicon nitride. .Iadd.19. A method for producing and filling an isolation groove in a semiconductor substrate, the substrate having a major surface and successive, doped and insulating layers formed in superposed relationship on the major surface for forming semiconductor devices therein and defining an upper surface of the substrate substantially parallel to the major surface of said substrate, the isolation groove having substantially parallel interior sidewalls, spaced apart and defining the width of the groove and extending, transversely to the upper surface, through the superposed insulating and doped layers and into the substrate and defining the depth of the groove and an interior bottom wall within the substrate, the depth of the groove being greater than the width thereof, comprising:
- (a) forming a mask layer on the upper surface of the semiconductor substrate, the mask layer having a window extending therethrough and exposing a portion of the upper surface of the semiconductor substrate at which an isolation groove is to be formed;
- (b) etching the successive, doped and insulating layers and the semiconductor substrate in the respective portions thereof, as exposed in succession through the mask layer during the etching, thereby to form the isolation groove;
- (c) thermally oxidizing the sidewalls and the bottom wall of the groove to form a first insulating layer as a coating on each of the sidewalls and the bottom wall;
- (e) etching the deposited polysilicon semiconductor material through the window in the mask for removing a portion of the deposited polysilicon semiconductor material from within the groove such that the resulting, exposed upper surface thereof is substantially at the aforesaid, defined depth location;
- (f) depositing insulating material on the substrate by a sputtering method or a chemical vapor deposition method, thereby both to fill the groove with a second insulating layer extending from said resulting, exposed upper surface of the deposited polycrystalline semiconductor material and thus from the aforesaid depth location and up to the major surface of the substrate, and also to bury the groove and the second insulating layer with further said insulating material; and
- (g) etching said further insulating material while employing the mask layer as an etching stopper thereby to remove a portion of the further insulation material of said second insulating layer sufficient to expose the mask layer, thereby forming a common, flat upper surface of the second insulating layer and the exposed upper surface of the substrate..Iaddend. .Iadd.20. The method of claim 19, wherein the step of etching of the material of the second insulating layer comprises:
- wet or dry etching of the second insulating layer, as filled in the isolation groove by a sputtering method, to provide the common, flat upper surface of the second insulating layer and the exposed upper surface of the substrate..Iaddend. .Iadd.21. The method of claim 19, wherein the step of etching of the material of the second insulating layer comprises:
- chemically polishing the second insulating layer, as filled in the isolation groove by a chemical vapor deposition method, to provide the common, flat upper surface of the second insulating layer and the exposed upper surface of the substrate..Iaddend.
Priority Claims (1)
Number |
Date |
Country |
Kind |
57-171977 |
Sep 1982 |
JPX |
|
Parent Case Info
.Iadd.
This is a continuation of copending application Ser. No. 07/078,752 filed on Jul. 28, 1987, now abandoned, which is a reissue application of U.S. Pat. No. 4,509,249. .Iaddend.
US Referenced Citations (9)
Foreign Referenced Citations (1)
Number |
Date |
Country |
34942 |
Mar 1983 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Abbas, S. A., "Recessed Oxide Isolation Process," IBM Technical Disclosure Bulletin, vol. 20, No. 1, Jun. 1977. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
78752 |
Jul 1987 |
|
Reissues (1)
|
Number |
Date |
Country |
Parent |
535342 |
Sep 1983 |
|