BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a top view, schematically illustrating a layout of an array of non-volatile memory.
FIG. 2 is a cross-sectional view, schematically illustrating a conventional structure of the memory cell along the cross-section direction X1 in FIG. 1.
FIG. 3 is a cross-sectional view, schematically illustrating the conventional structure of the memory cell along the cross-section direction X2 in FIG. 1.
FIG. 4 is a top view, schematically illustrating a layout of an array of another non-volatile memory.
FIG. 5 is a cross-sectional view, schematically illustrating a conventional structure of the memory cell along the cross-section direction X3 in FIG. 4.
FIG. 6 is a cross-sectional view, schematically illustrating the conventional structure of the memory cell along the cross-section direction X4 in FIG. 4.
FIGS. 7A-7D are cross-sectional views, schematically illustrating the processes for forming a non-volatile memory, according to an embodiment of the invention.
FIGS. 8A-8D are cross-sectional views, schematically illustrating the processes for forming a non-volatile memory, according to another embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the invention, a novel non-volatile memory is proposed, so that the leakage current from the isolation region between the word lines can be effectively reduced, and the accessing error can be therefore reduced. Several embodiments are provided for description of the invention. However, the invention is not just limited to the embodiments.
FIGS. 7A-7D are cross-sectional views, schematically illustrating the processes for forming a non-volatile memory, according to an embodiment of the invention. The layout of the non-volatile memory is similar to the layout in FIG. 1. However, due to the fabrication method of the present invention, the charge trapping layer is significantly removed at the isolation region, according to the investigation of leakage current by the invention. In FIGS. 7A-7D, the left cross-section views are along the cross-section direction X1 in FIG. 1, and the right cross-section views are along the cross-section direction X2 in FIG. 1.
In FIG. 7A, a substrate 200 is provided. Then, multiple bit lines 201 are formed in the substrate 200 at the memory area. Here, the fabrication at the peripheral area is not described. The bit lines 201 can be the doped lines in the substrate along a first direction. In addition, portions of each of the bit lines 201 serve as source/drain regions for a plurality of memory cells. A charge storage stacked layer 202 is formed over the substrate. The charge storage stacked layer 202 comprises a charge trapping layer 202b. In the usual structure, the charge storage stacked layer 202 include, for example, a bottom oxide layer 202a, a charge trapping layer 202b, and a top oxide layer 202c. The charge trapping layer 202b is, for example, nitride layer, Si rich silicon nitride layer (i.e SiN), tantalum oxide layer (i.e. Ta2O5), aluminum oxide layer (i.e. Al2O3) or nano-crystal silicon layer. In general, any kind of material capable of trapping charge can be used.
A conductive layer 204 is formed over the charge storage layer 202. The conductive layer 204 can be, for example, polysilicon layer, and can be formed by, for example, chemical vapor deposition (CVD). Then, a mask layer 206 is formed on the conductive layer 204. The mask layer 206 can be, for example, a photoresist layer with a pattern, correspond to the word lines (WL). In other words, the mask layer 206 is not at the cross-section direction X2 at the right drawing. The pattern of mask layer 206 includes multiple lines along another direction, intersecting with the bit lines 201.
In FIG. 7B, a first etching process is performed on the conductive layer 204 with the mask layer 206, so as to form a plurality of word lines (WL), which is a remaining portion of the conductive layer 204 at the cross-section direction X1 (see left drawing) but not at the cross-section direction X2 (see right drawing). It should be noted that portions of each of the word lines (WL) 204 between the bit lines 201 serve as gate electrodes for the memory cells. Since the conductive layer 204, such as the polysilicon, has the different etching ratio to the dielectric layer of the charge storage stacked layer 202 with the top oxide dielectric layer 202c, the first etching process may stop on the top oxide dielectric layer 202c.
A second etching process is further needed to etch the charge storage stacked layer 202 at the portion not covered by the mask layer 206. Remarkably, in general, at least a portion of the charge trapping layer 202b not being covered by the mask layer 206 is removed. In other words, the bottom oxide layer 202a may still remain on the substrate 200. However, for the easy process, a proper etchant can be used to etch the oxide and nitride but not the silicon, so that the second etching can remove the charge storage stacked layer 202 without etching the substrate 200. In FIG. 7D, after removing the mask layer 206, the remaining portion of the conductive layer 204 has several word lines at the cross-section direction X1 but not at the cross-section direction X2. In this kind of non-volatile memory, a portion of the substrate 200 between the word lines and between the bit lines also serve as the isolation region. The isolation region is not covered by the charge trapping layer 202b. Alternatively, the region between the word lines has no the charge trapping layer 202b.
However, if the exposed portion of the substrate 200 between the word lines is necessary to be further protected, such as the situation shown in FIG. 7D, another protection oxide layer (not shown) can be optionally formed on the substrate 200 by, for example, thermal oxidation process. The protection oxide layer may also improve the isolation function.
In the invention as shown in FIG. 7D, there is no charge trapping layer existing the substrate 200 at the cross-section direction X2. The residual charges do not exit too. Therefore, the conventional leakage current for the non-volatile memory with doped bit lines in the substrate can be significantly reduced.
Remarkably, the features of the invention can also be apply to another design of non-volatile memory. For example, FIGS. 8A-8D are cross-sectional views, schematically illustrating the processes for forming a non-volatile memory, according to another embodiment of the invention. The processes in FIGS. 8A-8D are for forming the non-volatile memory based on the layout in FIG. 4. The non-volatile memory also includes the selection gate. However, the consideration on leakage current is the same as that in the layout of FIG. 1. The left drawings in FIGS. 8A-8D are along the cross-section direction X3 in FIG. 4 and the right drawings are along the cross-section direction X4 in FIG. 4.
In FIG. 8A, a substrate 300 is provided. A plurality of doped lines 302 is formed in the substrate along a first direction at the memory region. The doped lines 302 also serve as a plurality of bit lines 302 (BL0, BL1, BL1, . . . ). Portions of each of the doped lines 302 serve as source/drain regions for a plurality of memory cells. A plurality of stacked selection gate lines (SG0, SG1, . . . ), including the gate dielectric layer 304, the selection gate layer 306 and the cap layer 308, is formed on the substrate 300 along a first direction between the bit lines 302. The stacked selection gate lines can be formed by, for example, sequentially depositing a gate oxide layer, a polysilicon layer, and a cap layer, such as a nitride cap layer, over the substrate 300, and then the three layers are patterned by photolithographic and etching process into the gate dielectric layer 304, the selection gate layer 306 and the cap layer 308, between the bit lines 302. Here, the cap layer 308 is used to further improve the isolation the selection gate layer 306 from the word lines (WL) 312 because the ONO layer 310 is too thin.
Then, a charge storage stacked layer 310 is formed over the substrate 300, wherein the charge storage stacked layer 310 comprises, for example, a bottom oxide layer 310a, a charge trapping layer 310b, and a top oxide layer 310c. The charge storage stacked layer 310 also cover the sidewall an top surface of the stacked selection gate lines (SG0, SG1, . . . ). A conductive layer 312, such as a polysilicon layer, is formed over the substrate 300 on the charge storage stacked layer 310. The conductive layer 312 is to be patterned into the word lines (WL). For example, a mask layer 314 is formed over the conductive layer 312. The mask layer 314 is, for example, a photoresist layer with a pattern having multiple lines along another direction intersecting with the bit lines 302.
The mask layer 314 is used as the etching mask, and the etching process is performed to remove a portion of the conductive layer 312, not covered by the mask layer 314. As a result, the portion of the conductive layer at the cross-section direction X4 (right drawing) is removed to expose the charge storage stacked layer 310, while the portion of the conductive layer 312 at the cross-section direction X3 (left drawing) remains.
An etching back process is performed with the same mask layer 314, so that the exposed portion of the charge storage stacked layer 310 is removed. As a result, a spacer is formed on the sidewall of the stacked selection gate lines formed from the gate dielectric layer 304, the selection gate layer 306 and the cap layer 308. The spacer is the remaining portion of the charge storage stacked layer 310 due to the etching back process, as well known by the person with ordinary skill. Here, the spacer is, for example, shown with the remaining portion of the charge trapping 310b and the bottom oxide layer 310a. However, the remaining portion of the top oxide layer 310c is small portion and is not shown here. The spacer is naturally formed due to the etching back process as well known in conventional skill. Next in FIG. 8D, the mask layer 314 is removed. It should be also noted that the charge trapping layer 310b is significantly removed. However, another oxide layer may be optionally further formed to protect the exposed portion of the substrate 300.
The essential features to be noted here are that the charge trapping layer 310b at the cross-section direction X4 between the word lines WL is substantially removed except the portion in the spacer. Therefore, there is not charge trapping layer in the region 316. This can significantly reduce the accumulation of residual charges, and the therefore reduce the leakage current. The accessing error of the data is then reduced.
As can be seen from the foregoing embodiments, the invention has looked into the leakage current in the conventional fabrication process for the non-volatile memory with the bit line, doped in the substrate. The leakage current can be solved by the invention for these specific types of non-volatile memory. Since the leakage current can be significantly reduced, the accessing error is reduced, accordingly.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.
Patent Application
20080032470
