Claims
- 1. A method for fabricating a semiconductor device having a thin-film resistor, comprising:
- forming a semiconductor element in a semiconductor substrate;
- forming an insulating film on a surface of said semiconductor substrate;
- forming a contact hole to said semiconductor element in said insulating film;
- depositing a thin-film resistor material on said insulating film and in said contact hole formed in said insulating film;
- forming a barrier metal on said thin-film resistor material;
- forming a mask on said barrier metal;
- patterning said barrier metal by wet etching using said mask;
- light-etching the surface of said thin-film resistor material after said patterning of said barrier metal;
- after said light etching, patterning said deposited thin-film resistor material into a thin-film resistor by removing at least thin-film resistor material in said contact hole formed in said insulating film by means of chemical dry etching including patterning said thin-film resistor material into said thin-film resistor by chemical dry etching using said mask, said removing being performed in an etching chamber using radicals obtained by recombining ions generated in a plasma generation chamber, said etching chamber being separate from a plasma generation chamber; and
- forming electrodes contacting said thin-film resistor and contacting said semiconductor element via said contact hole.
- 2. The method according to claim 1, wherein said contact hole forming includes forming said contact hole by wet etching.
- 3. The method according to claim 1, wherein said contact hole forming includes forming said contact hole by dry etching.
- 4. The method according to claim 3, further comprising annealing to round the top of said contact hole after said dry etching.
- 5. The method according to claim 4, wherein said annealing is performed before said depositing of said thin-film resistor material.
- 6. The method according to any one of claims 1 through 5, wherein said depositing includes depositing a material of a compound containing Cr and Si.
- 7. The method according to any one of claims 1-5, wherein said barrier metal is TiW, and wherein said chemical dry etching uses CF.sub.4 and oxygen.
- 8. The method according to any one of claims 1-5, wherein said light-etching includes dipping said resistor material at room temperature for 15 seconds into an etching solution of H.sub.2 O.sub.2 :H.sub.2 O:NH.sub.4 OH=100:100:5.
- 9. A method for fabricating a semiconductor device having a thin-film resistor, the method comprising:
- forming a semiconductor element in a semiconductor substrate;
- forming an insulating film on a surface of said semiconductor substrate;
- depositing a thin-film resistor material on said insulating film;
- forming a barrier metal on said thin-film resistor material;
- patterning said barrier metal;
- patterning said deposited thin-film resistor material into a thin-film resistor by means of chemical dry etching;
- forming electrodes contacting said thin-film resistor and said semiconductor element; and
- light etching a surface of said thin-film resistor material after said patterning of said barrier metal;
- wherein said patterning of said thin-film resistor material into said thin-film resistor is performed after said light-etching.
- 10. The method according to claim 9, wherein said depositing includes depositing a material of a compound containing Cr and Si.
- 11. The method according to claim 9 wherein said barrier metal is TiW, and wherein said chemical dry etching uses CF.sub.4 and oxygen.
- 12. The method according to claim 9, wherein said light-etching includes dipping said resistor material at room temperature for 15 seconds into an etching solution of H.sub.2 O.sub.2 :H.sub.2 O:NH.sub.4 OH=100:100:5.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-126115 |
Jun 1994 |
JPX |
|
CROSS REFERENCE TO RELATED APPLICATION
This is a continuation of application Ser. No. 08/463,550, filed Jun. 5, 1995, abandoned.
This application is based upon and claims the benefit of priority of the prior Japanese Patent application No. 6-126115 filed on Jun. 8, 1994, the contents of which are incorporated herein by reference.
US Referenced Citations (12)
Foreign Referenced Citations (18)
Number |
Date |
Country |
0350961 |
Jan 1990 |
EPX |
0443575 |
Aug 1991 |
EPX |
63-229717 |
Sep 1983 |
JPX |
59-214240 |
Dec 1984 |
JPX |
60-261101 |
Dec 1985 |
JPX |
3-8368 |
Jan 1986 |
JPX |
63-096948 |
Apr 1988 |
JPX |
63-119549 |
May 1988 |
JPX |
63-227047 |
Sep 1988 |
JPX |
2-58259 |
Feb 1990 |
JPX |
2-20364 |
Dec 1990 |
JPX |
3-012960 |
Jan 1991 |
JPX |
3-104118 |
May 1991 |
JPX |
4-44259 |
Feb 1992 |
JPX |
4-44260 |
Feb 1992 |
JPX |
5-029547 |
Feb 1993 |
JPX |
5-90501 |
Apr 1993 |
JPX |
5-211357 |
Aug 1993 |
JPX |
Non-Patent Literature Citations (5)
Entry |
John L. Vossen and Werner Kern, Thin Film Processes II, 1991. |
S. M. Sze, VLSI Technology, 1988. |
S.Wolf, "Silicon Processing for the VLSI Era," vol. II 1990, pp. 103-110, 192, 335, Jun. 1990. |
Translation of JP 2-104118, May 1991. |
S.Wolf & R.N. Tauber, "Silicon Processing for the VLSI Era," vol. I, pp. 541,542, 581, Jun. 1990. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
463550 |
Jun 1995 |
|