The invention relates to the field of semiconductor manufacturing, and more specifically, the invention describes a new technique for electrochemical unplating or plating/deposition of micro and nano-scale patterns. The invention describes a procedure that is a potential substitute for lithography.
There exist today several innovative manufacturing technologies to meet the demand for the production of components with features in the range of a sub-micron to several hundred micrometers. They are classified into two basic groups (Rajurkar et al, 2006): (i) lithography based micro fabrication processes, which are capable of micro and sub-micrometer size features, and (ii) micro manufacturing processes, which are capable of micro and miniaturized part fabrications. Unfortunately, we are rapidly approaching the limit of traditional processing methods for functionalizing and processing inexpensive miniaturized devices. Clearly, a major challenge remains in the micro-manufacturing community to develop flexible, robust and large-scale fabrication methods that are economical and also environmentally friendly.
Traditionally, the lithography based processes employ either material addition (e.g., Physical Vapor Deposition “PVD,” Chemical Vapor Deposition “CVD,” and electro-deposition) or material subtraction (e.g., UV and e-beam lithography) to produce micron and submicron scale surface patterning. However, such processes are naturally limited by macro-scale phenomenon such as diffusion or thermal gradients. Any patterning scheme utilizing deposition methods must create and maintain a tight gradient (in the nanometer range) in driving force to control deposition and transport rates. Although subtraction processes such as electron or ion beam writing possess very high resolution capabilities for local patterning, they are sequential and cumbersome (due to macro-scale positioning requirements) with limitations in the materials they can modify and strict requirements of surface planarity. Thus, direct extension of lithographic based fabrication facility, with its attendant high cost of ownership (COO) and the required capital outlay of upwards of $3 billion are somewhat impractical for miniaturized components for targeting inexpensive and rapid throughput.
For example, the MicroStepper described by Miller et al. (2000) can achieve sub-100-nm patterning, but the equipment is expensive and requires planarized surfaces with roughness of the order of 0.1 times the wavelength of the ultraviolet light.
Non-lithographic based processes can also be classified as additive and subtractive processes (see Rajurkar et al., 2006 and the references therein for an exhaustive list of processes). Out of this list, we focus our attention on mechanical micromachining vs. electro-physical and chemical processes (ECP). In mechanical micromachining, a direct contact with the work piece is established, with good geometric correlation between the tool path and the work piece. While they possess high material removal rate, these methods, however, are not suitable for very hard or very fragile, e.g., low dielectric porous materials. In addition, they induce significant level of residual stresses, and possess additional limitations on dimensional tolerances and minimum gage requirements (Liu et al, 2004). On the other hand, ECP offer distinct advantages by not contacting the work-piece, especially in electro-discharge machining (EDM) and electrochemical machining (ECM). The ECP eliminates the drawback due to elastic spring back and the minimum gage requirement to sustain the cutting forces. In addition, they are quite economical for small batch productions (IWF, 2002). The ECP processes have been successfully employed in aerospace, automobile, and other industries for shaping, cutting, debarring and finishing. These processes provide solutions for manufacturing small and very precise components and micro-systems for the watch industry, micro-optics (telecommunications), medicine (processing biocompatible materials, medical implants) and chemical industry (micro-reactors).
ECM process can provide excellent performance for large and contoured surfaces. It also provides low material waste and very little tool wear. Complex shapes ranging from hard to machine titanium and wasp alloys aircraft engine casings (McGeough, 1974), to miniaturized LIGA processes are common utilization of ECM (Friedrich et al., 1997; Dunkel et al., 1998, Craston et al., 1988; Husser et al., 1989). While the EC process has found major applications in IC fabrications such as in Damascene Cu Plating (Andricacos, 1999) and in electrochemical mechanical planarization of wafers (Steigerwald et al., 1997; Huo et al., 2004), most ECM processes, however, are not environmentally benign. They also give rise to thermal and environmental concerns. The finished surface comes in contact with corrosive chemicals, which may accelerate corrosion and necessitate post-ECM cleaning of the finished surface (Wilson, 1971). Maintaining an ECM tool over a long period of time has also proved difficult.
The electrochemical process described by Mazur et al. (2005) is environmentally benign. However, it is only meant for polishing or planarization, and cannot imprint a specified pattern on a surface.
The traditional lithography or other contact printing processes also require extremely tight tolerances in surface roughness and planarization. This makes surface preparation for such processes quite expensive, often requiring chemical mechanical planarization “CMP.”
Thus, capability for printing on wavy surfaces is also required for flexible IC devices, where performing CMP is very difficult. Therefore, there is a need in the industry for a device that produces sub-100-nm patterns through a non-contact process. The conventional available devices that can produce such patterns are expensive, and also typically require polished or planarized surfaces.
The disclosed invention provides a Focused Electric Field Imprinting (FEFI) process. It is a variation of the electrochemical unplating process wherein the process is adapted for imprinting range of patterns of around 20-2000 microns in width and 0.1-10 microns in depth. A suitably curved proton exchange membrane and/or curved electrode are key elements of some embodiments of the process. By altering mask-membrane interaction parameters and process settings, one can significantly reduce the feature size and possibly generate sub-100-nm features. By using a mesh or mask as the electrode behind the membrane in the electrochemical cell, the feature generation process is parallelized. Using a sequence of such FEFI steps, and proper mask alignment, one can also generate sub-100-nm lines with sub-100-nm spacing. The described FEFI process has been implemented on copper substrate, but the process works equally well on any electrical conductor. FEFI is provided as a cost-advantaged alternative to lithographic techniques.
In this patent application we specifically focus on creating patterns on bulk copper substrate or on a thin layer of copper that is deposited on a substrate. The disclosed process is also applicable to any electrically conducting surfaces. The described FEFI technique of the present invention can imprint on wavy surfaces. Thus, in microelectronic processing, it can potentially eliminate the CMP process step. In other industries such as heat exchangers and injection molding dies, FEFI process can generate three dimensional micron and submicron size features on wavy surfaces. FEFI tools of the present invention are also expected to be a factor of 10 to 100 less expensive.
The device described in this patent application utilizes a non-contact electrochemical process that can produce specified patterns of around few microns in size. With appropriate consumables and process settings, production of sub-100-nm patterns is possible. Furthermore, this device can produce the above patterns on wavy surfaces, thereby relaxing the highly planarized surface requirement (Mazur et al., 2005).
Currently, Deep Ultraviolet (DUV) Steppers are used for Lithography. The cost of a manual DUV Stepper is of the order of $250,000, and an automatic DUV Stepper may cost up to $10,000,000. The estimated cost of the device described in this patent application is $10,000 for a manual version and $100,000 for an automatic version.
A DUV Stepper needs a planarized surface (Mazur et al., 2005) where, in some embodiments, the surface roughness may not exceed 0.1 times the wavelength of the ultraviolet light. The device described in this patent application relaxes the planarization requirement by a factor of 100 to roughly 1000.
The device of the present invention can produce circular and linear imprints or a combination of them to generate two-dimensional patterns on the substrate. A modification of the basic set-up can produce imprints that are either an array of circles or a number of parallel lines with different edge profile. With appropriate masks, it can produce imprints in any arbitrary closed or connected shapes. The number of circular imprints or the number of line imprints is easy to control and scalable for large-area arrays or for continuous on-line operation.
i is a cross-section view of the resulting substrate 99 having copper patterns or traces 91 remaining.
Although the following detailed description contains many specifics for the purpose of illustration, a person of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the following preferred embodiments of the invention are set forth without any loss of generality to, and without imposing limitations upon the claimed invention. Further, in the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized, and that structural, sequential, and temporal changes may be made without departing from the scope of the present invention.
The leading digit(s) of reference numbers appearing in the Figures generally corresponds to the Figure number in which that component is first introduced, such that the same reference number is used throughout to refer to an identical component that appears in multiple Figures. Trailing letters appending reference numbers generally refer to variations of embodiments regarding a component or process. Signals and connections may be referred to by the same reference number or label, and the actual meaning will be clear from its use in the context of the description.
As used herein “unplate” or “unplating” (though not in the present disclosure, this was sometimes informally called “etching” in U.S. Provisional Patent Application No. 60/804,163 filed by the inventors of the present invention) means a process of electrolytically removing material (such as one or more metals) from the substrate of interest. As used herein “plate” or “plating” means a process of electrolytically adding material (such as one or more metals) to the substrate of interest. Plating and unplating may use water, or acids or salts in a suitable solvent such as water. As used herein “wet etching” means a process of using strong acid to remove material from the unprotected parts of a metal surface to create a pattern by removing metal from the substrate of interest (and may or may not also include applying an electrical current). As used herein “dry etching” means a process such as bombarding a metal with ions (such as reactive-ion etching (“RIE”) or deep reactive-ion etching (“DRIE”)) to remove material from the unprotected parts of a metal surface to create a pattern by removing metal from the substrate of interest. As used herein “etching” includes wet etching and/or dry etching.
The Devices
In some other embodiments, a thicker and/or stiffer membrane 112 is used, in order to provide a slightly-conforming surface of membrane 112, which contacts only the highest points of conductor 99. This provides a way of planarizing a copper layer 95 on substrate 99 that is a non-abrasive-contact alternative to chemical-mechanical polishing (CMP). Thus, in some embodiments, the present invention provides a membrane 112 that is sufficiently thick and/or stiff so as to conform to a minority (i.e., less than about 50%) of the surface of substrate 99 opposite the membrane 112. In various other embodiments, membrane 112 is sufficiently thick and/or stiff so as to conform to about 40% or less, about 30% or less, about 20% or less, or about 10% or less, respectively, of the surface of substrate 99 opposite the membrane 112. (Mazur et al. 2005 uses a conventional device but for planarization only. The present invention for patterning and for conforming to wavy or uneven surfaces distinguishes from that.) In some embodiments, the micro- or nano-roughness of copper layer 95 is smoothed, while the larger scale waviness is maintained or not substantially disturbed. In contrast, conventional systems need to be planarized to achieve very small smoothness (e.g., smoothness to one-tenth the wavelength of UV light (i.e., 20 to 40 nanometers). The cell 110 need not move, and, in some embodiments, a thin layer of DI water remains between membrane 112 and copper layer 95 during the un-plating (or the inverse of plating) operation. In other embodiments, a pattern 120 is to be imprinted on the wavy surface 98 of substrate 99, and so a photoresist-defined mask layer 118 having one or more openings 116 is deposited on the top wavy surface (that follows wavy surface 98) of the copper or other metal layer 95. Note that the unplating operation is not performed to the entire substrate 99, but only to those portions that are contacted by membrane 112. In some embodiments, de-ionized water is applied in and between openings 116 and membrane 112. In some embodiments, electrolyte 111 is a solution of a suitable chemical (such as a metal salt dissolved in water) that removes one or more metals that are unplated through holes 116 and from conductive surface 95 when the electric current forces ions of the metal(s) through membrane 112.
In other embodiments, the “mask” in the present invention is a topographical pattern that is behind the membrane (i.e., distal from the surface being unplated) or on a front surface of the membrane (i.e., proximal to the surface being unplated) in the electrolytic cell. In some such embodiments, the mask is formed on a surface of membrane 112, and made of a suitably flexible non-conductive and/or ion-blocking material (such as photoresist) that is applied to the membrane 112 and patterned (e.g., silk-screened onto the surface through a stencil, or applied as a photoresist and then patterned using conventional photolithography). In some embodiments, features on the mask are planar or are formed to assume a concave or convex shape, in order that the shape is used to further focus the electric field, depending on the direction of the Faradic current flow for unplating or deposition. Also, in some embodiments, the mask is not photo-resist based, but can be produced by other micro machining techniques such as fiber weaving, laser or other surface manipulation techniques, or by depositing through a stencil such as is done in silk-screening processes.
As an alternative to CMP where mechanical pressure or motion is required to assist the chemical action to remove the copper and where a planarized surface may be required in order to be able to CMP, some embodiments of the present invention use the conforming surface of membrane 112 to provide a well-defined and uniform electric field over openings 116 to remove by unplating (or add by plating) predictable and controllable amounts of copper. In some embodiments (e.g., device 110′ of
In
When the membrane 212 remains horizontal, the electric field lines are vertical straight lines joining the membrane (cathode) 212 and the substrate (anode) 99. However, when the membrane is curved, the field lines 230 also are curved as shown in
When the electrolytic cell 210 is a vertical circular cylinder, the waist and consequently the imprinting are also circular. When the electrolytic cell is a horizontal half-circular cylinder, the waist and consequently the imprinting are long, slender rectangles. The aspect ratio of this rectangle can be different from the aspect ratio of the cylinder.
In
In some embodiments, the mask could be an electrically conductive material and act as the electrode. In other embodiments, the mask could be an electrically nonconductive material and an electrode has to be inserted into the electrolyte cavity 211. In yet another embodiment, the mask could be made of an electrical semiconductor material. In some embodiments of such a scenario, a pulsed DC voltage is used.
In some embodiments, rather than a mask of weaved wire mesh or perforated sheet, a membrane-support substrate 336 having deep-etched grooves or holes is used to support the membrane 312. When the electrolytic cell 310 includes a support substrate 337 (see
In some embodiments, the present invention does not use a separate proton-exchange membrane, but simply uses an electrode formed by micro-machining or nano-machining a substrate into a desired electrode shape having flat, convex, and/or concave shapes on its surface. The formed electrode can be used by itself if the substrate can be immersed in the electrolyte solution. Another embodiment is to spin coat the ion conducting layer 312 directly onto the machined electrode 336 in
i shows a cross-section view of the resulting substrate 99 having copper patterns or traces 91 remaining and openings or holes 92 where the copper was removed by the present invention.
In
In some such embodiments, the invention uses a periodic flush to remove any debris that is produced by the unplating process. In some embodiments, the debris is sucked up through the membrane into the CuSO4 solution in the electrolytic cell, and this solution is replaced periodically. Thus, a scratch-free, clean surface is provided on the electrode and the device being unplated.
In all embodiments, the applied DC voltage should be high enough such that the kinetics of the electrode reactions is not limiting the rate of the faradic process. In other embodiment, a chopped DC voltage is utilized to improve the material removal rate. The chopping rate should be of the same order of the electric boundary layer build up at the anode interface.
Example for FEFI Device
Using an apparatus equivalent to that shown in and described with reference to
The FEFI Experiment
Special care is necessary, in some embodiments, for controlling the exact distance between the device (cathode) and the substrate (anode). Another requirement, in some embodiments, is that the device and the substrate should be parallel. In some embodiments, to ensure such accuracy, motorized actuators are used.
In some embodiments, the present invention provides a Focused Electric Field Imprinting (FEFI) method that includes electrolytically transporting (i.e., removing or depositing) selected portions of a metal layer wherein an electric field is focused by a concave curvature surface or a convex curvature surface of a proton-exchange membrane, or by a curved electrode behind the membrane.
In other embodiments, the present invention provides a second method that includes providing a substrate having a conductive layer; forming a concave surface facing the conductive layer of the substrate; immersing the substrate and concave surface in a liquid; and applying an electric field between the concave surface and the conductive layer to remove selected portions of the conductive layer.
In some embodiments of the second method, the liquid is de-ionized water located between the conductive surface and the concave surface.
In some embodiments of the second method, the forming of the concave surface includes applying a pressure differential across a constrained membrane.
In some embodiments of the second method, the conductive surface includes copper or other electrically conductive substrates, the method further comprising applying an electrolyte solution (copper sulfate solution in the case of copper substrate) to a surface of the ion conducting membrane distal to the conductive substrate. In some embodiments, the membrane conducts copper ions through it.
In yet other embodiments, the present invention provides a third method that includes providing a substrate having a conductive layer; forming a convex surface facing the conductive layer of the substrate; immersing the substrate and convex compliant surface in a liquid; and applying an electric field between the convex surface and the conductive layer to remove a pattern of selected portions of the conductive layer.
In some embodiments of the third method, the third method is used for patterning conductor surfaces.
In some embodiments of the third method, the method is used to both planarize (using a convex membrane) and patternize (using a concave membrane).
Some embodiments of the third method further include using a weaved wire mesh or perforated mask behind the membrane in order to perform the method in a parallelized manner.
In some embodiments of the third method, the method further includes suitably curving the membrane and adjusting its stand-off distance, in order that the image of the mask is reduced.
In some embodiments of the third method, 20-2000-micron images with 0.1-10-micron depth are produced. In various embodiments, the present invention produces devices having features (i.e., as images on the devices) with lateral dimensions of about 200 microns or less, of about 150 microns or less, of about 125 microns or less, of about 100 microns or less, of about 90 microns or less, of about 80 microns or less, of about 70 microns or less, of about 60 microns or less, of about 50 microns or less, of about 40 microns or less, of about 30 microns or less, of about 20 microns or less, of about 15 microns or less, of about 12.5 microns or less, of about 10 microns or less, of about 9 microns or less, of about 8 microns or less, of about 7 microns or less, of about 6 microns or less, of about 5 microns or less, of about 4 microns or less, of about 3 microns or less, of about 2 microns or less, of about 1.5 microns or less, of about 1.25 microns or less, of about 1 microns or less, or of about 0.5 microns or less. In combination with any of the above, various embodiments of the present invention provide or produce devices having features (i.e., as images on the devices) with depth dimensions of about 50% of the minimum lateral dimensions, depth dimensions of about 40% of the minimum lateral dimensions, depth dimensions of about 30% of the minimum lateral dimensions, depth dimensions of about 20% of the minimum lateral dimensions, depth dimensions of about 10% of the minimum lateral dimensions, depth dimensions of about 5% of the minimum lateral dimensions, depth dimensions of about 3% of the minimum lateral dimensions, depth dimensions of about 2% of the minimum lateral dimensions, or depth dimensions of about 1% of the minimum lateral dimensions.
In some embodiments of the third method, sub-100 nm lines with about 5 micron pitch are possible to be produced using a single setting.
In some embodiments of the third method, the forming of the convex surface facing the conductive layer of the substrate; the immersing the substrate and convex compliant surface in a liquid; and the applying of the electric field between the convex surface and the conductive layer are repeated in a sequence that also includes mask alignments, in order to produce sub-100-nm lines with sub-100-nm spacing.
In some embodiments of the third method, the providing of the substrate includes providing a substrate having a surface with a surface roughness of at least about 100 times a wavelength of visible light.
In some embodiments of the third method, the providing of the substrate includes providing a substrate having a wavy surface with a surface waviness of at least about one hundred times a wavelength of visible light in order to imprint on the wavy surface, wherein the substrate is suitable for flexible electronics circuits.
In some embodiments, FEFI is a low-cost alternative to the current lithographic techniques used in Integrated Circuit manufacturing. Compared to Deep Ultraviolet (DUV) lithography tools, FEFI will significantly contribute to the cost reduction in VLSI/ULSI fabrication.
Micromachining,
and
Microfabrication, vol. 2, SPIE, Bellingham,
Mechanical
Planarization
of
Microelectronic
Materials.
This application is a divisional of U.S. patent application Ser. No. 11/811,288, filed on Jun. 7, 2007, titled “METHOD AND APPARATUS FOR FOCUSED ELECTRIC-FIELD IMPRINTING FOR MICRON AND SUB-MICRON PATTERNS ON WAVY OR PLANAR SURFACES” (which issued as U.S. Pat. No. 7,998,323 on Aug. 16, 2011), which claimed benefit under 35 U.S.C. 119(e) of U.S. Provisional Patent Application No. 60/804,163, filed on Jun. 7, 2006, titled “METHOD AND APPARATUS FOR FOCUSED ELECTRIC-FIELD IMPRINTING FOR MICRON AND SUB-MICRON PATTERNS ON WAVY OR PLANAR SURFACES,” each of which is incorporated herein by reference in its entirety.
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Number | Date | Country | |
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60804163 | Jun 2006 | US |
Number | Date | Country | |
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Parent | 11811288 | Jun 2007 | US |
Child | 13210372 | US |