METHOD FOR FORMING A BIT LOG-LIKELIHOOD RATIO FROM SYMBOL LOG-LIKELIHOOD RATIO

Abstract

In an OFDM (Orthogonal frequency-division multiplexing) communication system, a receiver comprising an inner forward error correction device, or an inner forward error correction device is provided. Either the inner forward error correction device, or the outer forward error correction device comprises an improved method for deriving a bit log-likelihood ratio derived from a symbol log-likelihood ratio. The method includes the steps of: providing two simplified parameters; and using the two simplified parameters in addition and subtraction only to derive the bit log-likelihood ratio derived from the symbol log-likelihood ratio.

Description

FIELD OF THE INVENTION

The present invention relates generally to communication devices. More specifically, the present invention relates to a bit log-likelihood ratio derived from a symbol log-likelihood ratio.

BACKGROUND

OFDM (Orthogonal frequency-division multiplexing) is known. U.S. Pat. No. 3,488,445 to Chang describes an apparatus and method for frequency multiplexing of a plurality of data signals simultaneously on a plurality of mutually orthogonal carrier waves such that overlapping, but band-limited, frequency spectra are produced without casing interchannel and intersymbol interference. Amplitude and phase characteristics of narrow-band filters are specified for each channel in terms of their symmetries alone. The same signal protection against channel noise is provided as though the signals in each channel were transmitted through an independent medium and intersymbol interference were eliminated by reducing the data rate. As the number of channels is increased, the overall data rate approaches the theoretical maximum. OFDM transreceivers are known. U.S. Pat. No. 5,282,222 to Fattouche et al describes a method for allowing a number of wireless transceivers to exchange information (data, voice or video) with each other. A first frame of information is multiplexed over a number of wideband frequency bands at a first transceiver, and the information transmitted to a second transceiver. The information is received and processed at the second transceiver. The information is differentially encoded using phase shift keying. In addition, after a pre-selected time interval, the first transceiver may transmit again. During the preselected time interval, the second transceiver may exchange information with another transceiver in a time duplex fashion. The processing of the signal at the second transceiver may include estimating the phase differential of the transmitted signal and pre-distorting the transmitted signal. A transceiver includes an encoder for encoding information, a wideband frequency division multiplexer for multiplexing the information onto wideband frequency voice channels, and a local oscillator for upconverting the multiplexed information. The apparatus may include a processor for applying a Fourier transform to the multiplexed information to bring the information into the time domain for transmission.

Using PN (pseudo-noise) as the guard interval in an OFDM is known. U.S. Pat. No. 7,072,289 to Yang et al describes a method of estimating timing of at least one of the beginning and the end of a transmitted signal segment in the presence of time delay in a signal transmission channel. Each of a sequence of signal frames is provided with a pseudo-noise (PN) m-sequences, where the PN sequences satisfy selected orthogonality and closures relations. A convolution signal is formed between a received signal and the sequence of PN segments and is subtracted from the received signal to identify the beginning and/or end of a PN segment within the received signal. PN sequences are used for timing recovery, for carrier frequency recovery, for estimation of transmission channel characteristics, for synchronization of received signal frames, and as a replacement for guard intervals in an OFDM context.

Under known conditions, a decoder needs to accurately decode the original code. However, due to channel fading, and other factors, the probability of the received signal being correct varies symbol by symbol. For example, in 64 QAM a symbol possesses 8 levels. Therefore, good symbols should be given increased weight. Therefore, it is desirous to have improved decoding accuracy by introducing channel state information to a compution of LLR. However, the introduction of the channel state information increases computation complexity. Therefore, reducing said complexity is desirable.

SUMMARY OF THE INVENTION

A method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions is provided.

A method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions using only two parameters as inputs is provided.

A method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio by introducing channel state information into a LLR computation is provided.

A method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio by increasing the weight to a symbol if said symbol possess a higher probability of being correct into a LLR computation is provided.

In an OFDM (Orthogonal frequency-division multiplexing) communication system, an improved method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions is provided.

In an OFDM communication system, an improved method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions using only two parameters as inputs is provided.

In an OFDM (Orthogonal frequency-division multiplexing) communication system, wherein at least one modulation scheme is possible, an improved method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions is provided.

In an OFDM communication system, wherein at least one modulation scheme is possible, an improved method for a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions using only two parameters as inputs is provided.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.

FIG. 1 is an example of a receiver in accordance with some embodiments of the invention.

FIG. 2 is an example of a block diagram of the present invention.

FIG. 3 is a first example of a decoder structure of the present invention.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

DETAILED DESCRIPTION

Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method steps and apparatus components related to a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions. Accordingly, the apparatus components and method steps have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processors and unique stored program instructions that control the one or more processors to implement, in conjunction with certain non-processor circuits, some, most, or all of the functions of a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions described herein. The non-processor circuits may include, but are not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. As such, these functions may be interpreted as steps of a method to perform a computation of bit log-likelihood ratio from the symbol log-likelihood ratio using only addition and subtraction actions. Alternatively, some or all functions could be implemented by a state machine that has no stored program instructions, or in one or more application specific integrated circuits (ASICs), in which each function or some combinations of certain of the functions are implemented as custom logic. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such software instructions and programs and ICs with minimal experimentation.

Referring to FIG. 1, a receiver 10 for implementing a LDPC based TDS-OFDM communication system is shown. In other words, FIG. 1 is a block diagram illustrating the functional blocks of an LDPC based TDS-OFDM receiver 10. Demodulation herein follows the principles of TDS-OFDM modulation scheme. Error correction mechanism is based on LDPC. The primary objectives of the receiver 10 is to determine from a noise-perturbed system, which of the finite set of waveforms have been sent by a transmitter and using an assortment of signal processing techniques reproduce the finite set of discrete messages sent by the transmitter.

The block diagram of FIG. 1 illustrates the signals and key processing steps of the receiver 10. It is assumed the input signal 12 to the receiver 10 is a down-converted digital signal. The output signal 14 of receiver 10 is a MPEG-2 transport stream. More specifically, the RF (radio frequency) input signals 16 are received by an RF tuner 18 where the RF input signals are converted to low-IF () or zero-IF signals 12. The low-IF or zero-IF signals 12 are provided to the receiver 10 as analog signals or as digital signals (through an optional analog-to-digital converter 20).

In the receiver 10, the IF signals are converted to base-band signals 22. TDS-OFDM (Time domain synchronous-Orthogonal frequency-division multiplexing) demodulation is then performed according to the parameters of the LDPC (low-density parity-check) based TDS-OFDM modulation scheme. The output of the channel estimation 24 and correlation block 26 is sent to a time de-interleaver 28 and then to the forward error correction block. The output signal 14 of the receiver 10 is a parallel or serial MPEG-2 transport stream including valid data, synchronization and clock signals. The configuration parameters of the receiver 10 can be detected or automatically programmed, or manually set. The main configurable parameters for the receiver 10 include: (1) Sub carrier modulation type: QPSK, 16 QAM, 64 QAM; (2) FEC rate: 0.4, 0.6 and 0.8; (3) Guard interval: 420 or 945 symbols; (4) Time de-interleaver mode: 0, 240 or 720 symbols; (5) Control frames detection; and (6) Channel bandwidth: 6, 7, or 8 MHz.

The functional blocks of the receiver 10 are described as follows.

Automatic gain control (AGC) block 30 compares the input digitized signal strength with a reference. The difference is filtered and the filter value 32 is used to control the gain of the amplifier 18. The analog signal provided by the tuner 12 is sampled by an ADC 20. The resulting signal is centered at a lower IF. For example, sampling a 36 MHz IF signal at 30.4 MHz results in the signal centered at 5.6 MHz. The IF to Baseband block 22 converts the lower IF signal to a complex signal in the baseband. The ADC 20 uses a fixed sampling rate. Conversion from this fixed sampling rate to the OFDM sample rate is achieved using the interpolator in block 22. The timing recovery block 32 computes the timing error and filters the error to drive a Numerically Controlled Oscillator(not shown) that controls the sample timing correction applied in the interpolator of the sample rate converter.

There can be frequency offsets in the input signal 12. The automatic frequency control block 34 calculates the offsets and adjusts the IF to baseband reference IF frequency. To improve capture range and tracking performance, frequency control is done in two stages: coarse and fine. Since the transmitted signal is square root raised cosine filtered, the received signal will be applied with the same function. It is known that signals in a TDS-OFDM system include a PN sequence preceding the IDFT symbol. By correlating the locally generated PN with the incoming signal, it is easy to find the correlation peak (so the frame start can be determined) and other synchronization information such as frequency offset and timing error. Channel time domain response is based on the signal correlation previously obtained. Frequency response is taking the FFT of the time domain response.

In TDS-OFDM, a PN sequence replaces the traditional cyclic prefix. It is thus necessary to remove the PN sequence and restore the channel spread OFDM symbol. Block 36 reconstructs the conventional OFDM symbol that can be one-tap equalized. The FFT block 38 performs a 3780 point FFT. Channel equalization 40 is carried out to the FFT 38 transformed data based on the frequency response of the channel. De-rotated data and the channel state information are sent to FEC for further processing.

In the TDS-OFDM receiver 10, the time-deinterleaver 28 is used to increase the resilience to spurious noise. The time-deinterleaver 28 is a convolutional de-interleaver which needs a memory with size B*(B−1)*M/2, where B is the number of the branch, and M is the depth. For the TDS-OFDM receiver 10 of the present embodiment, there are two modes of time-deinterleavering. For mode 1, B=52, M=240, and for mode 2, B=52, M=720.

The LDPC decoder 42 is a soft-decision iterative decoder for decoding, for example, a Quasi-Cyclic Low Density Parity Check (QC-LDPC) code provided by a transmitter (not shown). The LDPC decoder 42 is configured to decode at 3 different rates (i.e. rate 0.4, rate 0.6 and rate 0.8) of QC_LDPC codes by sharing the same piece of hardware. The iteration process is either stopped when it reaches the specified maximum iteration number (full iteration), or when the detected error is free during error detecting and correcting process (partial iteration).

The TDS-OFDM modulation/demodulation system is a multi-rate system based on multiple modulation schemes (QPSK, 16 QAM, 64 QAM), and multiple coding rates (0.4, 0,6, and 0.8), where QPSK stands for Quad Phase Shift Keying and QAM stands for Quadrature Amplitude Modulation. The output of BCH decoder is bit by bit. According to different modulation scheme and coding rates, the rate conversion block combines the bit output of BCH decoder to bytes, and adjusts the speed of byte output clock to make the receiver 10's MPEG packets outputs evenly distributed during the whole demodulation/decoding process.

The BCH decoder 46 is designed to decode BCH (762, 752) code, which is the shortened binary BCH code of BCH (1023, 1013). The generator polynomial is x̂10+x̂3+1.

Since the data in the transmitter has been randomized using a pseudo-random (PN) sequence before BCH encoder (not shown), the error corrected data by the LDPC/BCH decoder 46 must be de-randomized. The PN sequence is generated by the polynomial 1+x¹⁴+x¹⁵, with initial condition of 100101010000000. The de-scrambler/de-randomizer 48 will be reset to the initial condition for every signal frame. Otherwise, de-scrambler/de-randomizer 48 will be free running until reset again. The least significant 8-bit will be XORed with the input byte stream.

The data flow through the various blocks of the modulator is as follows. The received RF information 16 is processed by a digital terrestrial tuner 18 which picks the frequency bandwidth of choice to be demodulated and then downconverts the signal 16 to a baseband or low-intermediate frequency. This downconverted information 12 is then converted to the Digital domain through an analog-to-digital data converter 20.

The baseband signal after processing by a sample rate converter 50 is converted to symbols. The PN information found in the guard interval is extracted and correlated with a local PN generator to find the time domain impulse response. The FFT of the time domain impulse response gives the estimated channel response. The correlation 26 is also used for the timing recovery 32 and the frequency estimation and correction of the received signal. The OFDM symbol information in the received data is extracted and passed through a 3780 FFT 38 to obtain the symbol information back in the frequency domain. Using the estimated channel estimation previously obtained, the OFDM symbol is equalized and passed to the FEC decoder.

At the FEC decoder, the time-deinterleaver block 28 performs a deconvolution of the transmitted symbol sequence and passes the 3780 blocks to the inner LDPC decoder 42. The LDPC decoder 42 and BCH decoders 46 which run in a serial manner take in exactly 3780 symbols, remove the 36 TPS symbols and process the remaining 3744 symbols and recover the transmitted transport stream information. The rate conversion 44 adjusts the output data rate and the de-randomizer 48 reconstructs the transmitted stream information. An external memory 52 coupled to the receiver 10 provides memory thereto on a predetermined or as needed basis.

Referring to FIG. 2, at either inner LDPC decoder 42 or outer BCH decoders 46 a computation of bit log-likelihood ratio from the symbol log-likelihood ratio is required. For reliability-based soft-decision decoding algorithms or methods suitable of computer implementation developed recently, such as turbo-decoding, or LDPC decoding, etc., the inputs to the decoder generally consist of log likelihood ratios (LLRs) determined by or based upon channel statistics. For the most common modulation/demodulation system currently in use, there are generally multiple modulation methods, which exist simultaneously. Therefore, an effective FEC decoder should be capable of simultaneously decoding channel-corrupted signals for multiple kinds or modes of modulation. Furthermore, the effective FEC decoder should be capable of reducing the hardware cost or footprint to a minimum.

The present invention contemplates a method or device, which introduce channel state information and derive two common factors (α,β) for simplifying the calculation after the introduction of the channel state information in calculating bit log-likelihood-ratio from symbol log-likelihood-ratio for different bits in different modulation schemes or modes such as 16 QAM, and 64 QAM. By sharing in a single module or device for computing these two common factors, the complication, or the complexity of the bit LLR computation circuits are substantially reduced, thereby significantly reducing the hardware implementation cost.

Returning now to FIG. 2, a block diagram 60 of the present invention is shown. Diagram 60 comprises an α-β computing block 62 having α and β as output. The input to block 62 comprises Y, L_c, and c_si. Where Lc=2/σ² with σ being the standard deviation of channel noise such as white noise. c_si is the channel state information, and Y is the transformed frequency value of the sum of c_si channel state information and a noise. In other words, Y is the frequency reponse of an input signal limited by the combined channel response function H(f). Channel state information may be presented or obtained in the form of correlating with the received channel responding sequence with known PN sequence used in channel estimation. This way, the BER (bit error rate) vs. SNR performance is greatly improved. In other words, using the inherent nature of c_si channel state information as a correction factor is desirous. However, using the c_si channel state information outright introduces heavy computations including multiple divisions and multiplications. By introducing into the computations of either α, or β, the computations reduced to merely additions and subtractions thereby greatly reducing the computations process.

If a first received symbol has a greater probability of being correct, a larger value of c_si channel state information is added thereto, thereby reinforcing the decoding device. Therefore, an accurately transmitted signal has a better chance of be correctly decoded because of the introduction of the c_si channel state information. Computing block 62 is coupled to a simplified computing circuit 64 having α and β as input. Circuit 64 consist of only addition and subtraction actions therein, thereby rendering the computation simple in nature. Circuit 64 further has an input flag FEC_mode 66 for controlling the mode of the simple computation therein. The result of the simple computation or the outputs of circuit 64 are respectively Lb₀, Lb₁, and Lb₂, respectively for this particular case.

Returning now to FIG. 3, a LDPC based FEC (forward error correction) decoder structure 70 is provided. Computation block 72 denotes the I channel computation of the present invention. Computation block 74 denotes the Q channel computation of the present invention. Both bock 74 and block 72 may use the method of the present invention. The parallel computed results of the present invention are formed into a serial stream by block 76. The serial stream LDPC block which is similar to block 42 of FIG. 1. The resultant output in turn is subjected to BCH block 80, which is similar to block 46 of FIG. 1. Than, the stream is subjected to bit/byte block 82, which is similar to rate conversion block 44 of FIG. 1. Lastly, the stream is subjected to de-randomization block 84, which is similar to descramble block 48 of FIG. 1.

The procedure for deriving the α and β is as follows. Note the elaborate mathematical processes that require more than mere addition and subtraction actions. First for 64 QAM, the mapping schemes are using Grey Mapping, which are listed in table 1.

TABLE 1
64QAM Greying Mapping
S0	000	−7
S1	001	−5
S2	010	−1
S3	011	−3
S4	100	+7
S5	101	+5
S6	110	+1
S7	111	+3

The computation of Cmp_lb

In transmitter, the signals sent to a channel can be expressed as follows:

S=I+jQ   1.1

For 64 QAM, I and Q are mapped to −7, −5, −3, −1, 1, 3, 5, and 7. After channel (fading and AWGN), the received symbols can be expressed as:

R=S*CSI+N   1.2

Where CSI is called the Channel State Information, and N is the AWGN noise.

For each received symbol, the symbol probability is

$\begin{array}{cc}P\left(Y_tS_i\right)=\exp \left[-\frac{L_c}{4}*{\left(R-S*\mathrm{CSI}\right)}^2\right]& 1.3\end{array}$

Where

$\begin{array}{cc}{L}_c=\frac{2}{\mathrm{noise\_power}}=\frac{2}{21*{10}^{-0.1*\mathrm{snr}}}& 1.4\end{array}$

Sym2bit

Sym2bit module generates the bit probability according to the received symbol probability incorporating channel state information (CSI).

For 64 qam,

$\begin{array}{cc}\begin{array}{c}L\left(b_1\right)=\log \frac{\sum _{x_t\in x_i^{b_1}}^{}p\left(y_tx_t\right)P\left(x_t\right)}{\sum _{x_t\in x_i^{b_0}}^{}p\left(y_t|x_t\right)P\left(x_t\right)}\\ =\log \frac{\begin{array}{c}\begin{array}{c}\begin{array}{c}p\left(y_ts_1\right)p\left(b_3=0\right)p\left(b_2=0\right)p\left(b_1=1\right)+\\ p\left(y_ts_3\right)p\left(b_3=0\right)p\left(b_2=1\right)p\left(b_1=1\right)+\end{array}\\ p\left(y_t|s_5\right)p\left(b_3=1\right)p\left(b_2=0\right)p\left(b_1=1\right)+\end{array}\\ p\left(y_t|s_7\right)p\left(b_3=1\right)p\left(b_2=1\right)p\left(b_1=1\right)\end{array}}{\begin{array}{c}\begin{array}{c}\begin{array}{c}p\left(y_ts_0\right)p\left(b_3=0\right)p\left(b_2=0\right)p\left(b_1=0\right)+\\ p\left(y_ts_2\right)p\left(b_3=0\right)p\left(b_2=1\right)p\left(b_1=0\right)+\end{array}\\ p\left(y_t|s_4\right)p\left(b_3=1\right)p\left(b_2=0\right)p\left(b_1=0\right)+\end{array}\\ p\left(y_t|s_6\right)p\left(b_3|=1\right)p\left(b_2=1\right)p\left(b_1=0\right)\end{array}}\\ =\log [\frac{p\left(b_1=1\right)}{p\left(b_1=0\right)}·\frac{\begin{array}{c}p\left(y_ts_1\right)+p\left(y_ts_3\right)\frac{P\left(b_2=1\right)}{p\left(b_2=0\right)}+\\ p\left(y_ts_5\right)\frac{P\left(b_3=1\right)}{p\left(b_3=0\right)}+p\left(y_ts_7\right)\frac{P\left(b_2=1\right)}{p\left(b_2=0\right)}\frac{P(b_3=}{p(b_3=}\end{array}}{\begin{array}{c}p\left(y_ts_0\right)+p\left(y_ts_2\right)\frac{p\left(b_2=1\right)}{p\left(b_2=0\right)}+\\ p\left(y_ts_4\right)\frac{p\left(b_3=1\right)}{p\left(b_3=0\right)}+p\left(y_ts_6\right)\frac{P\left(b_2=1\right)}{p\left(b_2=0\right)}\frac{P(b_3=}{p(b_3=}\end{array}}\end{array}& 1.5\\ \begin{array}{c}L\left(b_2\right)=\log \frac{\sum _{x_t\in x_i^{b_2}}^{}p\left(y_tx_t\right)P\left(x_t\right)}{\sum _{x_t\in x_i^{b_2}}^{}p\left(y_t|x_t\right)P\left(x_t\right)}\\ =\log \frac{\begin{array}{c}p\left(y_ts_2\right)p\left(b_3=0\right)p\left(b_2=1\right)p\left(b_1=0\right)+\\ p\left(y_ts_3\right)p\left(b_3=0\right)p\left(b_2=1\right)p\left(b_1=1\right)+\\ p\left(y_t|s_6\right)p\left(b_3=1\right)p\left(b_2=1\right)p\left(b_1=0\right)+\\ p\left(y_t|s_7\right)p\left(b_3|=1\right)p\left(b_2=1\right)p\left(b_1=1\right)\end{array}}{\begin{array}{c}\begin{array}{c}\begin{array}{c}p\left(y_ts_0\right)p\left(b_3=0\right)p\left(b_2=0\right)p\left(b_1=0\right)+\\ p\left(y_ts_1\right)p\left(b_3=0\right)p\left(b_2=0\right)p\left(b_1=1\right)+\end{array}\\ p\left(y_t|s_4\right)p\left(b_3=1\right)p\left(b_2=0\right)p\left(b_1=0\right)+\end{array}\\ p\left(y_t|s_5\right)p\left(b_3=1\right)p\left(b_2=0\right)p\left(b_1=1\right)\end{array}}\\ =\log [\frac{p\left(b_2=1\right)}{p\left(b_2=0\right)}·\frac{\begin{array}{c}p\left(y_ts_2\right)+p\left(y_ts_3\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}+\\ p\left(y_ts_6\right)\frac{P\left(b_3=1\right)}{p\left(b_3=0\right)}+p\left(y_ts_7\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}\frac{P(b_3=}{p(b_3=}\end{array}}{\begin{array}{c}p\left(y_ts_0\right)+p\left(y_ts_1\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}+\\ p\left(y_ts_4\right)\frac{P\left(b_3=1\right)}{p\left(b_3=0\right)}+p\left(y_ts_5\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}\frac{P(b_3=}{p(b_3=}\end{array}}\end{array}& 1.6\\ \begin{array}{c}L\left(b_3\right)=\log \frac{\sum _{x_t\in x_i^{b_3}}^{}p\left(y_tx_t\right)P\left(x_t\right)}{\sum _{x_t\in x_i^{b_3}}^{}p\left(y_t|x_t\right)P\left(x_t\right)}\\ =\log \frac{\begin{array}{c}p\left(y_ts_4\right)p\left(b_3=1\right)p\left(b_2=0\right)p\left(b_1=0\right)+\\ p\left(y_ts_5\right)p\left(b_3=1\right)p\left(b_2=0\right)p\left(b_1=1\right)+\\ p\left(y_t|s_6\right)p\left(b_3=1\right)p\left(b_2=1\right)p\left(b_1=0\right)+\\ p\left(y_t|s_7\right)p\left(b_3=1\right)p\left(b_2=1\right)p\left(b_1=1\right)\end{array}}{\begin{array}{c}\begin{array}{c}\begin{array}{c}p\left(y_ts_0\right)p\left(b_3=0\right)p\left(b_2=0\right)p\left(b_1=0\right)+\\ p\left(y_ts_1\right)p\left(b_3=0\right)p\left(b_2=0\right)p\left(b_1=1\right)+\end{array}\\ p\left(y_t|s_2\right)p\left(b_3=0\right)p\left(b_2=1\right)p\left(b_1=0\right)+\end{array}\\ p\left(y_t|s_3\right)p\left(b_3=0\right)p\left(b_2=1\right)p\left(b_1=1\right)\end{array}}\\ =\log [\frac{p\left(b_3=1\right)}{p\left(b_3=0\right)}·\frac{\begin{array}{c}p\left(y_ts_4\right)+p\left(y_ts_5\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}+\\ p\left(y_ts_6\right)\frac{P\left(b_2=1\right)}{p\left(b_2=0\right)}+p\left(y_ts_7\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}\frac{P(b_2=}{p(b_2=}\end{array}}{\begin{array}{c}p\left(y_ts_0\right)+p\left(y_ts_1\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}+\\ p\left(y_ts_2\right)\frac{P\left(b_2=1\right)}{p\left(b_2=0\right)}+p\left(y_ts_{35}\right)\frac{P\left(b_1=1\right)}{p\left(b_1=0\right)}\frac{P(b_2=}{p(b_2=}\end{array}}\text{indicates text missing or illegible when filed}\end{array}& 1.7\end{array}$

According to equation 7.3, and if we define

α=2·L_c·CSI·y_t   1.8

β=L_c·CSI²   1.9

When calculating L(b_i), we assume

$\frac{p\left(b_i=1\right)}{p\left(b_i=0\right)}=1$

here, otherwise, for some iterative decoding algorithm, like turbo decoder, which uses bit extrinsic information, Lb_in(i), from previous iteration,

$\begin{array}{cc}\frac{p\left(b_i=1\right)}{p\left(b_i=0\right)}=\exp \left({\mathrm{Lb}}_{in}\left(i\right)\right),i=1,2,3\mathrm{If}\frac{p\left(b_i=1\right)}{p\left(b_i=0\right)}=1,\mathrm{Equations}1.5,1.6,\mathrm{and}1.7\mathrm{can}\mathrm{be}\mathrm{simplified}\mathrm{as}& 1.10\\ L\left(b_1\right)=\log \frac{\begin{array}{c}\exp \left(-\frac{5}{4}\left(\alpha +5\beta \right)\right)+\exp \left(-\frac{3}{4}\left(\alpha +3\beta \right)\right)+\\ \exp \left(\frac{5}{4}\left(\alpha -5\beta \right)\right)+\exp \left(\frac{3}{4}\left(\alpha -3\beta \right)\right)\end{array}}{\begin{array}{c}\exp \left(\frac{-7}{4}\left(\alpha +7\beta \right)\right)+\exp \left(\frac{-1}{4}\left(\alpha +1\beta \right)\right)+\\ \exp \left(\frac{1}{4}\left(\alpha -\beta \right)\right)+\exp \left(\frac{7}{4}\left(\alpha -7\beta \right)\right)\end{array}}& 2.1\\ L\left(b_2\right)=\log \frac{\begin{array}{c}\exp \left(\frac{-1}{4}\left(\alpha +\beta \right)\right)+\exp \left(\frac{-3}{4}\left(\alpha +3\beta \right)\right)+\\ \exp \left(\frac{1}{4}\left(\alpha -\beta \right)\right)+\exp \left(\frac{3}{4}\left(\alpha +3\beta \right)\right)\end{array}}{\begin{array}{c}\exp \left(\frac{-7}{4}\left(\alpha +7\beta \right)\right)+\exp \left(\frac{-5}{4}\left(\alpha +5\beta \right)\right)+\\ \exp \left(\frac{7}{4}\left(\alpha -7\beta \right)\right)+\exp \left(\frac{5}{4}\left(\alpha -5\beta \right)\right)\end{array}}& 2.2\\ L\left(b_3\right)=\log \frac{\begin{array}{c}\exp \left(\frac{7}{4}\left(\alpha -7\beta \right)\right)+\exp \left(\frac{5}{4}\left(\alpha -5\beta \right)\right)+\\ \exp \left(\frac{1}{4}\left(\alpha -\beta \right)\right)+\exp \left(\frac{3}{4}\left(\alpha -3\beta \right)\right)\end{array}}{\begin{array}{c}\exp \left(\frac{-7}{4}\left(\alpha +7\beta \right)\right)+\exp \left(\frac{-5}{4}\left(\alpha +5\beta \right)\right)+\\ \exp \left(\frac{-1}{4}\left(\alpha +\beta \right)\right)+\exp \left(\frac{-3}{4}\left(\alpha +3\beta \right)\right)\end{array}}& 2.3\end{array}$

According to equations 2.1, 2.2, and 2.3, if we first calculate α, β, as well as S·(α−S·β), where S=±1,±3,±5,±7, we can easily find out L(b_i) by resource sharing, so that reducing many adders, sub-tractors, and multiplies.

As a result, the block diagram of Cmp_lb module is shown in FIG. 2. It includes Cmp_αβ block and Sym2bit block.

Cmp_αβ module computes 2 parameters α,β from the received symbol, Channel State Information (CSI) and Lc. Sym2bit module computes the actual Bit probability L(b_i) from the two parameters α, β according to different modulation mode.

For 16 QAM

TABLE 2
16QAM Grey Mapping
	S0	00	−3
	S1	01	−1
	S2	10	+3
	S3	11	+1

Similarly, for 16 qam, I and Q are mapped to −3, −1, 1, 3, also using Grey Mapping strategy, as shown in Table .2. The computation of bit probability can be expressed as

$\begin{array}{cc}L\left(b_1\right)=\log \frac{\exp \left(\frac{1}{4}\left(\alpha -1\beta \right)\right)+\exp \left(\frac{-1}{4}\left(\alpha +\beta \right)\right)}{\exp \left(\frac{-3}{4}\left(\alpha +3\beta \right)\right)+\exp \left(\frac{3}{4}\left(\alpha -3\beta \right)\right)}& 2.4\\ L\left(b_2\right)=\log \frac{\exp \left(\frac{3}{4}\left(\alpha -3\beta \right)\right)+\exp \left(\frac{1}{4}\left(\alpha -\beta \right)\right)}{\exp (\frac{-3}{4}\left(\alpha +3\beta \right)+\exp \left(\frac{-1}{4}\left(\alpha +\beta \right)\right)}& 2.5\end{array}$

They can also share the basic computation units with 64 qam calculation.

In an OFDM (Orthogonal frequency-division multiplexing) communication system, an improved method and apparatus for deriving a bit log-likelihood ratio derived from a symbol log-likelihood ratio comprising the steps of: providing two simplified parameters; and using the two simplified parameters in addition and subtraction only to derive the bit log-likelihood ratio derived from the symbol log-likelihood ratio.

It is noted that the present invention contemplates using the PN sequence disclosed in U.S. Pat. No. 7,072,289 to Yang et al which is hereby incorporated herein by reference.

In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

Claims

1. In an OFDM (Orthogonal frequency-division multiplexing) communication system, an improved method for deriving a bit log-likelihood ratio derived from a symbol log-likelihood ratio comprising the steps of: providing two simplified parameters; andusing the two simplified parameters in addition and subtraction only to derive the bit log-likelihood ratio derived from the symbol log-likelihood ratio.

2. The method of claim 1, wherein at least one PN (pseudo-noise) sequence is interposed between data packets suitable for transmission.

3. The method of claim 1, wherein the method is adapted for multi-mode modulations of at least two modes.

4. The method of claim 3, wherein the multi-mode modulation comprises 16 QAM mode.

5. The method of claim 3, wherein the multi-mode modulation comprises 64 QAM mode.

6. The method of claim 1, wherein the two simplified parameters simplifies at least three inputs into two, with the inputs comprising channel state information.

7. The method of claim 1, wherein the introduction of α and/or β reduces the computation resulting from the existing channel state information values.

8. In an OFDM (Orthogonal frequency-division multiplexing) communication system, a receiver comprising an inner forward error correction device, or an outer forward error correction device, either the inner forward error correction device, or the outer forward error correction device comprises an improved method for deriving a bit log-likelihood ratio derived from a symbol log-likelihood ratio, the method comprising the steps of: providing two simplified parameters; andusing the two simplified parameters in addition and subtraction only to derive the bit log-likelihood ratio derived from the symbol log-likelihood ratio.

9. The receiver of claim 8, wherein at least one PN (pseudo-noise) sequence is interposed between data packets suitable for transmission.

10. The receiver of claim 8, wherein the method is adapted for multi-mode modulations of at least two modes.

11. The receiver of claim 8, wherein the multi-mode modulation comprises 16 QAM mode.

12. The receiver of claim 8, wherein the multi-mode modulation comprises 64 QAM mode.

13. The receiver of claim 8, wherein the introduction of α and/or β reduces the computation resulting from the existing channel state information values.