| Number | Date | Country | Kind |
|---|---|---|---|
| 7-23582 | Feb 1995 | JPX |
This application is a continuation-in-part of Ser. No. 08/599,126 filed Feb. 9, 1996 now abandoned.
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| Entry |
|---|
| Y. Choi et al., "16Mbit Synchronous DRAM with 125Mbytes/sec Data Rate", 1993 Symposium on VLSI Circuits, May 1993, pp. 65-66. |
| S. Gowni et al., "A 9NS 32K X 9, BICMOS TTL Synchronous Cache Ram with Burst Mode Access", Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, May 3-6, 1992, pp. 781-784. |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 599126 | Feb 1996 |