Claims
- 1. A method for forming a strapless anti-fuse structure on a semiconductor substrate having a metal layer and having a layer of dielectric material deposited over said metal layer comprising:forming a first mask over said semiconductor substrate; exposing said first mask using photolithographic processes so as to define the location of an opening; etching said semiconductor substrate so as to form an opening extending through said first mask and extending through said dielectric layer, said opening exposing a portion of said metal layer; depositing a layer of electrically conductive material having a low melting temperature over said semiconductor substrate such that a portion of said layer of electrically conductive material overlies said layer of dielectric material and such that said layer of electrically conductive material is deposited within said opening in said layer of dielectric material; polishing said semiconductor substrate using a chemical mechanical polishing process so as to remove that portion of said layer of electrically conductive material that overlies said layer of dielectric material so as to form a plug within said opening in said layer of dielectric material such that said plug is electrically coupled to said metal layer; depositing a layer of amorphous silicon over said semiconductor substrate such that a portion of said layer of amorphous silicon overlies said plug; forming a second mask over said amorphous silicon layer; exposing said second mask using photolithographic processes to define the shape of an amorphous silicon block; etching said semiconductor substrate so as to form an amorphous silicon block having a top surface, a portion of said amorphous silicon block overlying said plug; depositing layer of aluminum over said semiconductor substrate such that said layer of aluminum directly overlies said top surface of said silicon block; forming a third mask over said layer of aluminum; exposing said third mask using photolithographic processes to define an interconnect; and etching said semiconductor substrate so as to remove portions of said layer of aluminum so as to form an aluminum interconnect such that a portion of said aluminum interconnect overlies said amorphous silicon block so as to form an anti-fuse, said anti-fuse allowing for electrical contact between said plug and said aluminum interconnect upon the engagement of said anti-fuse, said anti-fuse not having any intervening layers disposed between said top surface of said amorphous silicon block and said aluminum interconnect.
- 2. The method for forming a strapless anti-fuse structure of claim 1 wherein said amorphous silicon block has a height, said height of said amorphous silicon block determining the threshold voltage at which said anti-fuse is engaged such that, upon the application of current and a voltage greater than the threshold voltage between said plug and said interconnect, an electrical connection between said plug and said interconnect is formed.
- 3. The method for forming a strapless anti-fuse structure of claim 1 wherein said plug comprises tungsten.
- 4. The method for forming a strapless anti-fuse structure of claim 1 wherein said plug comprises titanium.
Parent Case Info
This is a divisional of copending application Ser. No. 08/878,707 filed on Jun. 19, 1997 is now a U.S. Pat. No. 6,016,001 which designated in the U.S.
US Referenced Citations (7)
Number |
Name |
Date |
Kind |
5374832 |
Tung et al. |
Dec 1994 |
A |
5514900 |
Iranmanesh |
May 1996 |
A |
5576576 |
Hawley et al. |
Nov 1996 |
A |
5592016 |
Go et al. |
Jan 1997 |
A |
5701027 |
Gordon et al. |
Dec 1997 |
A |
5763299 |
McCollum et al. |
Jun 1998 |
A |
5780323 |
Forouhi et al. |
Jul 1998 |
A |