Method for high-level synthesis of semiconductor integrated circuit

Abstract

A Control Data Flow Graph (CDFG) which is an intermediate representation obtained by analyzing a behavioral-level circuit description of hardware, is subjected to a process of changing a shape of the CDFG by adding an operation before or after scheduling, so as to conceal design information. A CDFG to which a hardware resource has been allocated may be subjected to a process of changing the allocation of the hardware resource.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart illustrating a method for high-level synthesis of a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a diagram illustrating a behavioral-level circuit description in the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 3 is a diagram illustrating a DFG generated in an intermediate representation generating step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 4 is a diagram illustrating a DFG scheduled in a scheduling step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 5 is a diagram illustrating a DFG whose shape is changed in a circuit concealing step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 6 is a diagram illustrating a DFG to which a hardware resource is allocated in an allocation step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 7 is a diagram illustrating an RTL circuit description which has been subjected to a concealment process and output in a circuit description output step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 8 is a diagram illustrating an RTL circuit description which has not been subjected to a concealment process.

FIG. 9 is a diagram illustrating an upper hierarchical layer circuit description output as concealed decryption information in a circuit description output step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 10 is a diagram illustrating a behavioral-level circuit description which has been subjected to a concealment process and output in the circuit description output step of the semiconductor integrated circuit high-level synthesis method of the first embodiment.

FIG. 11 is a flowchart illustrating a method for high-level synthesis of a semiconductor integrated circuit according to a second embodiment.

FIG. 12 is a diagram illustrating a DFG whose shape is changed in a circuit concealing step of the semiconductor integrated circuit high-level synthesis method of the second embodiment.

FIG. 13 is a diagram illustrating another DFG whose shape is changed in a circuit concealing step of the semiconductor integrated circuit high-level synthesis method of the second embodiment.

FIG. 14 is a flowchart illustrating a method for high-level synthesis of a semiconductor integrated circuit according to a third embodiment.

FIG. 15 is a diagram illustrating a DFG to which hardware resources have been allocated.

FIG. 16 is a diagram illustrating an RTL circuit structure inferred from the DFG of FIG. 15.

FIG. 17 is a diagram illustrating a DFG to which hardware resources have been allocated and whose shape has been changed in a circuit concealing step of the semiconductor integrated circuit high-level synthesis method of the third embodiment.

FIG. 18 is a diagram illustrating an RTL circuit structure inferred from the DFG of FIG. 17.

FIG. 19 is a flowchart illustrating a detail of a circuit concealing step of a method for high-level synthesis method of a semiconductor integrated circuit according to a fourth embodiment.

FIG. 20 is a diagram illustrating a DFG in which an addition operation is added in the circuit concealing step of the semiconductor integrated circuit high-level synthesis method of the fourth embodiment.

FIG. 21 is a diagram illustrating a DFG in which a multiplication operation is further added in the circuit concealing step of the semiconductor integrated circuit high-level synthesis method of the fourth embodiment.

Claims

1. A method for high-level synthesis of a semiconductor integrated circuit, comprising: an intermediate representation generating step of analyzing a circuit description at a behavioral level of hardware to generate a Control Data Flow Graph (CDFG) composed of a Data Flow Graph (DFG) representing a flow of an operation and data appearing in the description and a Control Flow Graph (CFG) representing a flow of control of an execution sequence of the operation;a scheduling step of allocating an execution sequence of each node of the CDFG to a state synchronizing with a clock, based on information about a design constraint of a desired hardware circuit and an available hardware resource;an allocation step of allocating a hardware resource for achieving a process to each node of the CDFG;a circuit concealing step of changing the CDFG or a result of the allocation in view of concealment of design information in an output circuit description; anda circuit description output step of outputting a circuit description and concealment decryption information based on a process result of each step.

2. The method of claim 1, wherein the changing of the CDFG in the circuit concealing step is to add an operation which guarantees the consistency of a process result, and the operation is an operation which is not present on the CDFG.

3. The method of claim 1, wherein the changing of the CDFG in the circuit concealing step is to add an operation which guarantees the consistency of a process result, and the operation is an operation which is present on the CDFG.

4. The method of claim 1, wherein the changing of the CDFG in the circuit concealing step is to add an operation which guarantees the consistency of a process result, and delays on paths between an input and an output of the CDFG generated in the intermediate representation generating step are analyzed, and the operation is added to a path having a short delay with priority.

5. The method of claim 1, wherein the changing of the CDFG in the circuit concealing step is to add an operation which guarantees the consistency of a process result, and delays on paths between an input and an output of the CDFG generated in the intermediate representation generating step are analyzed, and the operation is added to a path having a long delay with priority.

6. The method of claim 1, wherein the changing of the CDFG in the circuit concealing step is to add an operation which guarantees the consistency of a process result, and the scheduled CDFG generated in the scheduling step is analyzed, and the operation is added within a range in which a process cycle is not increased.

7. The method of claim 1, wherein the circuit concealing step includes allocating a node representing a constant of the changed CDFG to a hardware resource other than constants.

8. The method of claim 7, wherein the hardware resource other than constants is an input port.

9. The method of claim 1, wherein the circuit concealing step includes adding an operation to a node having a small input bit width of the CDFG, the operation creating an output value of the node.

10. The method of claim 1, wherein the circuit concealing step includes adding an operation to a constant node of the CDFG, the operation creating a constant value of the constant node.

11. The method of claim 1, wherein the changing of the CDFG in the circuit concealing step is to add an operation which guarantees the consistency of a process result, and the operation is created by reusing the hardware resource allocated in the allocation step.

12. The method of claim 11, wherein the circuit concealing step includes reusing a hardware resource in which a multiplexer for selecting an input has a small control delay, with priority.

13. The method of claim 11, wherein the circuit concealing step including reusing a hardware resource having a small input bit width with priority.

14. The method of claim 1, wherein the circuit concealing step including limiting the number of operations added in the CDFG in accordance with a predetermined criterion.

15. The method of claim 14, wherein the predetermined criterion is an upper limit of the number of added operations.

16. The method of claim 14, wherein the predetermined criterion is an upper limit of an area increase rate at which an area of a hardware resource required to execute the added operation increases a circuit area before performing the circuit concealing step.

17. The method of claim 14, wherein the predetermined criterion is a delay increase rate at which a delay required to execute the added operation increases a longest path of the CDFG.

18. The method of claim 1, wherein the circuit description output step includes outputting the circuit description which includes an assertion description for verifying whether or not a result of the added operation has a desired value.

19. The method of claim 1, wherein the circuit description output step includes outputting the circuit description at a behavioral level.

20. The method of claim 1, wherein the circuit description output step includes outputting the circuit description at a register transfer level.

21. The method of claim 1, wherein the circuit description output step includes outputting a circuit description in an upper hierarchical layer for decrypting the output circuit description as a separate file of concealment decryption information.

22. The method of claim 1, wherein a method for the added operation is provided as a database.