Claims
- 1. A multiple processor system containing at least two processors, wherein each of said processors comprises:
a pair of transmit counters for a transmit communication channel; a pair of receive counters for a receive communication channel; and a write-only communication link from a first processor to a second processor, said first processor transferring packets to said second processor via said communication link.
- 2. The system of claim 1, wherein said pair of transmit counters on said first processor comprises:
a first transmit counter which contains the number of transmitted data packets for said first processor; and a second transmit counter which contains the number of available receive buffers for said second processor.
- 3. The system of claim 2, wherein said pair of receive counters on said second processor comprises:
a first receive counter which contains the number of completed transfers for said first processor; and a second receive counter which contains the number of available receive buffers for said second processor.
- 4. The system of claim 3, wherein said first transmit counter in said first processor writes its current value to said first receive counter in said second processor after each data transfer from said first processor.
- 5. The system of claim 4, wherein said second receive counter in said second processor writes its current value to said second transmit counter in said first processor when receiving buffers are freed or reused on said second processor.
- 6. The system of claim 1, further comprising:
a second write-only communication link from said second processor to said first processor, said second processor transferring data packets, to said first processor via said second communication link.
- 7. A method for establishing a two-way communication link between a first processor and a second processor, both processors maintaining a pair of transmit counters for a transmit communication channel and a pair of receive counters for a receive communication channel, said method comprising the steps of:
establishing a first write-only communication link from said first processor to said second processor; and establishing a second write-only communication link from said second processor to said first processor.
- 8. The method of claim 7, wherein said pair of transmit counters on said first processor comprises:
a first transmit counter which contains the number of transmitted data packets for said first processor; and a second register counter to contain the number of available receive bufers for said second processor.
- 9. The method of claim 8, wherein said pair of receive counters on said second processor comprises:
a first receive counter which contains the number of completed transfers for said first processor; and a second receive counter which contains the number of available receive buffers for said second processor.
- 10. The method of claim 9, wherein the step of establishing a first write-only communication link from said first processor to said second processor further comprises the steps of:
initializing all counters on said first processor and said second processor to zero; performing initialization by said second processor; and transferring data packets from said first processor to said second processor, wherein said processor increments said first transmit counter after each transfer until said second transmit counter minus said first transmit counter is equal to zero.
- 11. The method of claim 10, wherein said step of performing initialization by said second processor further comprises the steps of:
allocating receive buffer space locally by said second processor; transferring the allocated addresses to said first processor; incrementing said second receive counter on said second processor by the number of local buffers; and writing the updated value of said second receive counter on said second processor to said second transmit counter on said first processor.
- 12. The method of claim 10, wherein the step of establishing a write-only communication link from said first processor to said second processor further comprises the steps of:
calculating, by said second processor, the number of completed transfers by subtraction of said first receive counter on said second processor from said second receive counter on said second processor; processing, by said second processor, said buffers according to the result of said step of calculating; and freeing or reusing processed buffers by said second processor.
- 13. The method of claim 9, wherein the step of establishing a write-only communication link from said second processor to said first processor further comprises the steps of:
performing initialization by said first processor; and transferring data packets from said second processor to said first processor, wherein said second processor increments said first transmit counter after each transfer until said second transmit counter minus said first transmit counter is equal to zero.
- 14. A multiple processor system, comprising:
a first chip; and a second chip:
wherein a first substantially write-only communication link is established from said first chip to said second chip using a write-only message-based link protocol.
- 15. The system of claim 14, wherein each chip comprises:
means to transfer memory from one chip to another chip; means to generate interrupts guaranteeing a speedy processing of issued commands; means to keep track of link state and perform house-keeping operations; and means to receive requests from other components and queue requests in internal memory buffers.
- 16. The system of claim 15, wherein said means to transfer memory is a data mover.
- 17. The system of claim 15, wherein said means to generate interrupts is a remote mailbox register.
- 18. The system of claim 15, wherein said means to keep track of link state is a general purpose timer.
- 19. The system of claim 15, wherein said means to receive requests is Lightning Data Transfer or Peripheral Component Interconnect bus bridges.
- 20. The system of claim 15, wherein said write-only message-based link protocol uses a link structure comprising:
four 64-bit counters starting at zero; a list of buffer addresses provided by a remote chip into which data packets are transferred by said means to transfer memory; and other information only accessible to said first chip.
- 21. The system of claim 20, wherein said 64-bit counters are incremented monotonically and never overflow while said link is operational.
- 22. The system of claim 15, wherein said communication link is established using link initiation and control commands, said control commands comprising:
a start command to start up said communication link; an init command to synchronize said communication link; a run command to start data transferring after said communication link is synchronized; a reset command to rest both chip counters to zero when a chip determines its peer is out of sync; and a stop command to cause a remote peer chip to immediately stop sending data across.
- 23. The system of claim 14, wherein a second substantially write-only communication link is established from said second chip to said first chip using said link protocol.
- 24. A method for establishing a write-only communication link from a first chip to a second chip using a link driver wherein each chip comprising a means to transfer memory, a means to generate interrupt, a means to keep track of said link, and a means to receive requests, said method comprising the steps of:
said first chip sending a start command to notify said second chip that said first driver is starting; said first chip sending an init command to said second chip to synchronize said communication link; said second chip receiving said init command from said first chip; said second chip sending a start command to synchronize said communication link; and said means to transfer memory sending a run command to start data transferring across said communication link.
- 25. The method of claim 24, wherein said means to transfer memory is a data mover.
- 26. The method of claim 24, wherein said means to generate interrupts is a remote mailbox register.
- 27. The method of claim 24, wherein said means to keep track of link state is a general purpose timer.
- 28. The method of claim 24, wherein said means to receive requests is Lightning Data Transfer or Peripheral Component Interconnect bus bridges.
- 29. The method of claim 24, wherein said link driver uses a link structure comprising:
four 64-bit counters starting at zero; a list of buffer addresses provided by a remote chip into which data packets are transferred by said means to transfer memory; and other information only accessible to said first chip.
- 30. The method of claim 29, wherein said 64-bit counters are incremented monotonically and never overflow while said link is operational.
- 31. The method of claim 28, further comprising the step of:
sending, by said first chip, a reset command to set all counters of both chips to zero when said first chip determines said second chip is out of sync.
- 32. The method of claim 24, further comprising the step of:
sending, by first chip, a stop command to cause said second chip to immediately stop sending data packets across said link.
- 33. The method of claim 24, wherein said communication link changes to a starting state after said first chip sending a start command.
- 34. The method of claim 24, wherein said communication link changes to a running state after said second chip sending a start command.
- 35. The method of claim 32, wherein said communication link changes to a not running state after said first chip sending a stop command.
- 36. The method of claim 32, wherein said communication link changes to a starting state after said first chip sending a reset command.
- 37. The method of claim 27, wherein said timer is started if said timer is not already running when said driver receives a data packet for transmission.
- 38. The method of claim 37, wherein said timer is started if said timer is not already running when a data packet is sent to a transmit function of said driver.
- 39. The method of claim 38, wherein said timer is stopped if a remote chip has processed some additional, but not necessarily all, previously transmitted data packet.
- 40. The method of claim 39, wherein said timer is restarted if not all transmitted data packets or packets queued for transmission have been processed by said remote chip.
- 41. The method of claim 27, wherein said timer has a value of 500 microseconds.
- 42. The method of claim 40, wherein said timer expires and interrupts and an explicit run command is queued to said means to transfer memory to cause said remote chip to process transmitted data packets.
- 43. A computer readable storage medium containing a computer readable code for operating a computer system to implement a method for establishing a two-way communication link between a first processor and a second processor, both-processors maintaining a pair of transmit counters for a transmit communication channel and a pair of receive counters for a receive communication channel, said method comprising the steps of:
establishing a first write-only communication link from said first processor to said second processor; and establishing a second write-only communication link from said second processor to said first processor.
- 44. The computer readable storage medium of claim 43, wherein said pair of transmit counters on said first processor consists of:
a first transmit counter which contains the number of transmitted data packets for said first processor; and a second register counter to contain the number of available receives for said second processor.
- 45. The computer readable storage medium of claim 44, wherein said pair of receive counters on said second processor consists of:
a first receive counter which contains the number of completed transfers for said first processor; and a second receive counter which contains the number of available receives for said second processor.
- 46. The computer readable storage medium of claim 45, wherein the step of establishing a first write-only communication link from said first processor to said second processor further comprises the steps of:
initializing all counters on said first processor and said second processor to zero; performing initialization by said second processor; and transferring data packets from said first processor to said second processor, wherein said processor increments said first transmit counter after each transfer until said second transmit counter minus said first transmit counter is equal to zero
- 47. The computer readable storage medium of claim 46, wherein said step of performing initialization by said second processor further comprises the steps of:
allocating receive buffer space locally by said second processor; transferring the allocated addresses to said first processor; incrementing said second receive counter on said second processor by the number of local buffers; and writing the updated value of said second receive counter on said second processor to said second transmit counter on said first processor.
- 48. The computer readable storage medium of claim 46, wherein the step of establishing a write-only communication link from said first processor to said second processor further comprises the steps of:
calculating, by said second processor, the number of completed transfers by subtraction of said first receive counter on said second processor from said second receive counter on said second processor; processing, by said second processor, said buffers according to the result of said step of calculating; and freeing or reusing processed buffers by said second processor.
- 49. The computer readable storage medium of claim 45, wherein the step of establishing a write-only communication link from said second processor to said first processor further comprises the steps of:
performing initialization by said first processor; and transferring data packets from said second processor to said first processor, wherein said second processor increments said first transmit counter after each transfer until said second transmit counter minus said first transmit counter is equal to zero.
- 50. The computer readable storage medium of claim 43 wherein said computer readable code can be downloaded over the Internet.
- 51. A computer readable storage medium containing a computer readable code for operating a computer system to implement a method for establishing a write-only communication link from a first chip to a second chip using a link driver wherein each chip comprising a means to transfer memory, a means to generate interrupt, a means to keep track of state of said write-only communication link, and a means to receive requests, said method comprising the steps of:
said first chip sending a start command to notify said second chip that said first driver is starting; said first chip sending an init command to said second chip to synchronize said communication link; said second chip receiving said init command from said first chip; said second chip sending a start command to synchronize said communication link; and said means to transfer memory sending a run command to start data transferring across said communication link.
- 52. The computer readable storage medium of claim 51, wherein said means to transfer memory is a data mover.
- 53. The computer readable storage medium of claim 51, wherein said means to generate interrupts is a remote mailbox register.
- 54. The computer readable storage medium of claim 51, wherein said means to keep track of link state is a general purpose timer.
- 55. The computer readable storage medium of claim 51, wherein said means to receive requests is Lightning Data Transfer or Peripheral Component Interconnect bus bridges.
- 56. The computer readable storage medium of claim 51, wherein said link driver uses a link structure comprising:
four 64-bit counters starting at zero; a list of buffer addresses provided by a remote chip into which data packets are transferred by said means to transfer memory; and other information only accessible to said first chip.
- 57. The computer readable storage medium of claim 56, wherein said 64-bit counters are incremented monotonically and never overflow while said link is operational.
- 58. The computer readable storage medium of claim 55, further comprising the step of:
sending, by said first chip, a reset command to set all counters of both chips to zero when said first chip determines said second chip is out of sync.
- 59. The computer readable storage medium of claim 51, further comprising the step of:
sending, by first chip, a stop command to cause said second chip to immediately stop sending data packets across said link.
- 60. The computer readable storage medium of claim 51, wherein said communication link changes to a starting state after said first chip sending a start command.
- 61. The computer readable storage medium of claim 51, wherein said communication link changes to a running state after said second chip sending a start command.
- 62. The computer readable storage medium of claim 59, wherein said communication link changes to a not running state after said first chip sending a stop command.
- 63. The computer readable storage medium of claim 59, wherein said communication link changes to a starting state after said first chip sending a reset command.
- 64. The computer readable storage medium of claim 54, wherein said timer is started if said timer is not already running when said driver receives a data packet for transmission.
- 65. The computer readable storage medium of claim 64, wherein said timer is started if said timer is not already running when a data packet is sent to a transmit function of said driver.
- 66. The computer readable storage medium of claim 65, wherein said timer is stopped if a remote chip has processed some additional, but not necessarily all, previously transmitted data packet.
- 67. The computer readable storage medium of claim 66, wherein said timer is restarted if not all transmitted data packets or packets queued for transmission have been processed by said remote chip.
- 68. The computer readable storage medium of claim 54, wherein said timer has a value of 500 microseconds.
- 69. The computer readable storage medium of claim 67, wherein said timer expires and interrupts and an explicit run command is queued to said means to transfer memory to cause said remote chip to process transmitted data packets.
- 70. The computer readable storage medium of claim 51, wherein said computer readable code can be downloaded over the Internet.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is related to pending U.S. patent application Ser. No. 09/679,115 filed on Oct. 4, 2000 (Attorney Docket No. AGLE0003).