Claims
- 1. A method of handling branches comprising:inputting a source program having one or more branch instructions to a compiler; compiling the source program to produce a machine-executable code, with a set of heuristics being applied to classify each of the one or more branch instructions as a hard-to-predict type or a simple type of branch, for running on a processor that includes first and second branch predictor circuits that operate on the hard-to-predict type and the simple type of branch instruction, respectively, the set of heuristics including identification of a conditional expression that specifies an array element access or a pointer reference.
- 2. The method according to claim 1 further comprising:marking in the machine-executable code each of the one or more branch instructions that satisfy the set of heuristics with a bit that identifies the branch instruction as the hard-to-predict type of branch.
- 3. The method according to claim 1 wherein the set of heuristics further includes a loop that traverses a linked data structure, or a loop that iterates more than a predetermined number of times.
- 4. A method of handling branch instructions comprising:compiling a source program that includes first and second branch instructions to produce an intermediate code; applying a set of heuristics to the intermediate code that classifies the first branch instruction as a hard-to-predict type, and the second branch instruction as a simple type; generating machine-executable code from the intermediate code, the machine-executable code including information which identifies the first branch instruction as the hard-to-predict type, for subsequent execution on a processor that includes first and second branch predictor circuits that operate on the hard-to-predict type and the simple type of branch instruction, respectively, the machine-executable code converting the first branch instruction into predicated execution code.
- 5. The method according to claim 4 wherein the information that identifies the first branch instruction as the hard-to-predict type comprises a hint bit.
- 6. A processor for executing a machine-executable code from a source code listing of the computer program, the machine-executable code including an identifier that classifies a branch instruction as either a hard-to-predict type or a simple type of branch instruction based on one or more heuristics including identification of a conditional expression that specifies an array element access or a pointer reference, the processor comprising:a first branch predictor circuit that predicts a target address of the hard-to-predict type of branch instruction; and a second branch predictor circuit that predicts a target address of the simple type of branch instruction.
- 7. The processor of claim 6 wherein the identifier comprises a hint bit.
- 8. The processor of claim 6 wherein the one or more heuristics includes a loop that traverses a linked data structure, or a loop that iterates more than a predetermined number of times.
- 9. A compiler for producing a machine-executable code from a source code listing of the computer program, comprising:a front-end that processes the source code listing and produces a high-level intermediate code that contains semantic information therefrom; an algorithm that operates on the high-level intermediate code to classify a branch instruction as either a hard-to-predict type or a simple type of branch instruction according to one or more heuristics which includes identification of a conditional expression that specifies an array element access or a pointer reference; an optimizer that converts the high-level intermediate code operated upon by the algorithm into a low-level intermediate code, a portion of the hard-to-predict type of branch instructions being converted into predicate execution code; a code generator that generates the machine-executable code from the optimized low-level intermediate code, a remaining portion of the hard-to-predict branch instructions being marked with a hint bit so that when the machine-executable code is run on a processor that includes first and second branch predictor circuits, the first branch predictor circuit operates on the hard-to-predict type of branch instruction, and the second branch predictor circuit operates on the simple type of branch instruction.
- 10. The compiler of claim 9 wherein the one or more heuristics further includes a loop that traverses a linked data structure or a loop that iterates more than a predetermined number of times.
Parent Case Info
This is a continuation of application Ser. No. 08/969,703, filed on Nov. 28, 1997, now U.S. Pat. No. 5,933,628, which is a continuation of application Ser. No. 08/699,827, filed on Aug. 20, 1996, now abandoned.
US Referenced Citations (16)
Non-Patent Literature Citations (2)
Entry |
Compiler-driven hybrid branch predictor, IBM technical disclosure bulletin, vol. 36, No. 2, Feb. 1993.* |
Polymorphic branch predictor, IBM technical disclosure bulletin, vol. 37, No. 7, Jul. 1994. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
08/969703 |
Nov 1997 |
US |
Child |
09/259980 |
|
US |
Parent |
08/699827 |
Aug 1996 |
US |
Child |
08/969703 |
|
US |