Patent Application
20120302049
1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to an ion implantation method for manufacturing semiconductors.
2. Description of the Related Art
In order to manufacture semiconductor devices, in particular semiconductor memory devices such as dynamic random access memories (DRAMs), numerous processes are carried out. Such processes include laminating, etching, ion implantation, etc., and are usually conducted on the base of a wafer unit. Among the unit processes, ion implantation is a process in which dopant ions such as boron and arsenic are accelerated by a strong electric field and are then passed through wafer surfaces. Therefore, electrical properties of materials can be modified via such ion implantation.
Ion implantation apparatuses for performing ion implantation methods include a source chamber for generating ions, an analyzer for selecting ions for implantation into a wafer among the generated ions, an acceleration tube for accelerating the selected ions so that the accelerated ions are implanted into the wafer at a desired depth, a beam focusing apparatus for focusing accelerated ion beams, a beam scanning plate for changing the direction of the ion beams to an upward, downward, left or right direction, a neutral beam trap for removing neutral beams included in the ion beams, an implantation chamber for implanting the ions into the wafer, and a vacuum device for providing a vacuum for the previously-mentioned elements. Ion implantation normally causes damage to the lattice structure of the wafer, and to remove the damage, the wafer is normally annealed at an elevated temperature, typically 600 to 1100•.
After the ions (impurities) are implanted into the wafer by the ion implanting apparatus, sheet resistance can be measured in order to estimate whether or not the ions have been properly implanted into the wafer.
The conventional process for wafer implantation typically requires a consistent dose or amount of ions for implantation into the wafer during the implanting process. However, since the process controllability of the implanting process applied in the peripheral annular portion of silicon wafer is inferior to that of the implanting process applied in the central circular portion of silicon wafer, the peripheral annular portion of a silicon wafer exhibits lower performance than the central circular portion of a silicon wafer under same process conditions (such as implanting conditions), thereby reducing the uniformity of electrical properties throughout all portions of the wafer.
Accordingly, implantation processes of a wafer do not result in uniform performances throughout all portions of the wafer. Thus, a need exists to develop new implantation process technology, which results in uniform performances throughout all portions of a wafer, following implantation.
The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different. Particularly, the ratio of the first average implantation dose and the second average implantation dose is of between 0.1-0.98 or between 1.02-10.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
The disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the disclosure. This description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the disclosure is best determined by reference to the appended claims.
The disclosure provides a method for wafer implantation, wherein the method includes the following steps. First, a wafer including a central circular portion, and a peripheral annular portion is provided, wherein the central circular portion and the peripheral annular portion are concentric. Next, the wafer is implanted by ion beams such that the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, wherein the first average implantation dose and the second first average implantation dose are different. The ion beams can include impurities to produce n or p type doped regions on the wafer 100, wherein the impurities can include antimony, arsenic or phosphorus to produce the n type doped regions, or include boron, gallium or indium to produce the p type doped regions on the wafer.
According to an embodiment of the invention, as shown in
In this embodiment, the implantation dose of the central circular portion 101 can be a fixed value equal to the set dose of the specific implanting process, since the central circular portion 101 exhibits good process controllability for implanting. Further, the set dose of the specific implanting process is optionally increased or reduced for the implanting dose of the peripheral annular portion 102 according to the process controllability of the peripheral annular portion 102. Therefore, the first average implantation dose D1 is not equal to the second average implantation dose D2 in order to achieve uniformity of electrical properties throughout all portions of the wafer 100 without degrading the performance of the central circular portion 101 of the wafer.
In an embodiment of the disclosure, still referring to
In an embodiment of the disclosure, the implantation dose of the wafer 100 can be gradually increased from the edge 104 to the center 103 of the wafer 100 or from the center 103 to the edge 104 of the wafer 100. In some embodiments of the disclosure, the implantation dose of the central circular portion 101 of the wafer 100 can be a fixed value, and/or the implantation dose of the peripheral annular portion 102 of the wafer 100 can a fixed value. Further, the implantation dose of the central circular portion 101 can be gradually increased or reduced from the edge 104 to the center 103 of the wafer 100, and the implantation dose of the peripheral annular portion 102 can be gradually increased or reduced from the edge 104 to the center 103 of the wafer 100.
Accordingly, the method for wafer implantation of the disclosure can be used to ensure uniformity of performance without degrading the performance of the central circular portion 101 of the wafer and improve the yield of subsequently processed semiconductors.
While the disclosure has been described by way of example and in terms of the preferred embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
