Claims
- 1. A method for manufacturing a semiconductor device on a substrate comprising:
- denuding by heating the substrate, wherein a denuded zone is created within the substrate;
- forming a pad oxide layer on the substrate;
- forming field oxide regions, wherein portions of the pad oxide layer in areas other than the field oxide regions form pad oxide regions;
- forming a screen oxide layer on the pad oxide regions; and
- implanting ions into the substrate after forming the screen oxide layer, wherein the screen oxide layer is sufficient to block a portion of the ions implanted into the substrate and is present over portions of the substrates in which ions are implanting into the substrate.
- 2. The method of claim 1 further comprising implanting ions into the substrate to form well regions within the substrate for the semiconductor device.
- 3. The method of claim 2 further comprising removing the screen oxide layer and forming a gate oxide layer and forming gate regions after removing the screen oxide layer.
- 4. The method of claim 3 further comprising forming gates for the semiconductor device in the gate regions.
- 5. The method of claim 1 further comprising annealing the semiconductor device after implanting ions into the substrate.
- 6. The method of claim 1 further comprising forming a pad oxide layer on the substrate prior to forming the screen oxide layer.
- 7. The method of claim 6 further comprising annealing the semiconductor device after implanting ions into the substrate.
- 8. The method of claim 7, wherein the annealing step is performed at a temperature from about 600.degree. C. to about 950.degree. C.
- 9. The method of claim 8, wherein the annealing step is performed in nitrogen gas.
- 10. The method of claim 1, wherein the denuding step is performed at a temperature from about 900.degree. C. to about 1150.degree. C.
- 11. The method of claim 6, wherein the pad oxide layer is from about 50 .ANG. to about 325 .ANG. thick.
- 12. The method of claim 1, wherein the screen oxide layer has a thickness from about 50 .ANG. to about 500 .ANG..
- 13. A method for manufacturing a semiconductor device on a silicon substrate comprising:
- denuding the substrate by heating the substrate, wherein a denuded zone is formed within the substrate;
- forming a pad oxide layer on the substrate;
- forming a nitride layer on the pad oxide layer;
- etching the nitride layer, wherein portions of the nitride layer remain as a remaining nitride layer and regions of exposed pad oxide are formed;
- forming field oxide regions in the regions of exposed pad oxide;
- removing the remaining nitride layer and exposing the pad oxide layer under the remaining nitride layer; performing ion implantation into the substrate and
- forming a screen oxide layer on the pad oxide layer prior to performing ion implantation, wherein the screen oxide layer remains in place over portions of the substrate in which ion implantation occurs.
- 14. The method of claim 13, wherein the step of performing ion implantation into the substrate after forming the screen oxide layer includes:
- implanting a buried layer of a first type of dopant;
- implanting a well using a dopant of the first type; and
- implanting a second well using a dopant of the second type.
- 15. The method of claim 14, wherein the step of implanting a buried layer using the first type of dopant comprises implanting P-type dopants at a dose from about 5e12 cm.sup.-2 to about 3e15 cm.sup.-2.
- 16. The method of claim 14, wherein the step of implanting a well using the second type of dopant comprises implanting a P-type dopant at a dose from about 5e10 cm.sup.-2 to about 2e13 cm.sup.-2.
- 17. The method of claim 14, wherein the step of implanting a well of the second type of dopant comprises implanting N-type dopants at a dose from about 5e12 cm.sup.-2 to about 3e14 cm.sup.-2 and then implanting N-type dopants at a dose from about 1e11 cm.sup.-2 to about 1e13 cm.sup.-2.
- 18. The method of claim 13, further comprising annealing the semiconductor device after the step of performing ion implantation.
- 19. The method of claim 18, wherein the annealing step is performed in nitrogen gas.
- 20. The method of claim 13 further comprising:
- performing a buried layer implant; and
- performing a retrograde implant and a channel stop implant to form a well within the denuded zone in the substrate.
- 21. The method of claim 20 further comprising annealing the semiconductor device after forming the well.
- 22. The method of claim 21 further comprising forming gates over the screen oxide layer.
- 23. The method of claim 13, wherein the pad oxide layer is from about 50 .ANG. to about 325 .ANG. thick.
- 24. The method of claim 13, wherein the screen oxide layer has a thickness from about 50 .ANG. to about 500 .ANG..
- 25. The method of claim 13, wherein the silicon substrate is a bulk silicon substrate.
- 26. A method for manufacturing a semiconductor device on a substrate comprising:
- denuding by heating the substrate, wherein a denuded zone is created within the substrate;
- forming a pad oxide layer on the substrate;
- forming field oxide regions, wherein portions of the pad oxide layer in areas other than the field oxide regions form pad oxide regions;
- forming a screen oxide layer on the pad oxide regions;
- implanting ions into the substrate after forming the screen oxide layer, wherein the screen oxide layer is sufficient to block a portion of the ions implanted into the substrate and is present over portions of the substrates in which ions are implanting into the substrate;
- forming a sacrificial oxide layer on the semiconductor device after implanting ions into the substrate; and
- forming a gate structure after forming the sacrificial oxide layer, wherein the gate structure has improved gate oxide integrity.
- 27. The method of claim 26 further comprising annealing the semiconductor device after implanting ions into the substrate and prior to forming a sacrificial gate oxide layer.
- 28. The method of claim 27 further comprising removing the pad oxide layer and the screen oxide layer after annealing the semiconductor device and prior to forming the sacrificial oxide layer.
Parent Case Info
This is a continuation of application Ser. No. 08/720,514 filed on Sep. 30, 1996, now abandoned.
US Referenced Citations (8)
Non-Patent Literature Citations (2)
Entry |
Wolf et al., Silicon Processing For the VLSI Era, Lattice Press, 1990, pp. 327-332, 423-424. |
Ghandi, VLSI Fabrication Principles, Wiley & Sons, 1983, pp. 353-354. |
Continuations (1)
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Number |
Date |
Country |
Parent |
720514 |
Sep 1996 |
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