1. Field of the Invention
The present invention relates generally to integrated circuit development, modeling and simulation and more specifically to improving accuracy of MOSFET models used in circuit simulation of integrated circuits.
2. Description of Related Art
An indispensable tool in the design of integrated circuits is the method of circuit simulation. The most familiar and commonly used circuit simulation tool is Berkeley SPICE and its commercial derivatives.
To run SPICE or other circuit simulation, the circuit designer provides a) a description of the circuit known as the netlist, b) chooses models for the various circuit elements and their parameter values, and c) specifies the desired analysis, which determines what kind of simulation will be performed in order to obtain the desired output, this set of SPICE commands is known as the input deck.
Active semiconductor devices such as MOSFETs are modeled using so-called compact models, analytic descriptions of device electrical behavior as a function of bias conditions as well as device geometry and doping. A number of compact MOSFET models have been proposed, the most popular models for submicron integrated circuit applications are currently the BSIM3 and newer BSIM4 model.
However, as MOSFET process technology moves deeper into the submicron region, the accuracy of circuit simulation using common circuit simulation tools such as SPICE in combination with standard compact device models such as BSIM3/4, greatly diminishes. The loss of accuracy occurs because the commonly used SPICE transistor models do not accurately capture 3-D effects, which become increasingly important in modern manufacturing processes. There are two primary reasons for the loss of MOSFET modeling accuracy:
One common technique used to improve modeling accuracy is to replace elements in question with more complex sub-circuits comprising several elements and designed to better represent the behavior of the actual physical device. An example application of such technique to improve MOSFET modeling accuracy at high frequencies is described in U.S. Pat. No. 6,618,837.
In designing an equivalent sub-circuit to account for physical pattern distortion effects in a MOSFET it is important to consider practical issues such as simulation efficiency and compatibility with existing circuit simulators. Excessive complexity of the resulting sub-circuit would significantly increase simulation times and may create numerical problems with existing circuit simulators making it impossible to use them in practical simulations. Models incompatible with existing compact models and circuit simulators would require new parameter extraction techniques to be devised and adopted.
Therefore a new practical approach to MOSFET modeling is needed that can accurately describe both nominal and statistical behavior of submicron devices, while relying as much as possible on the existing MOSFET modeling infrastructure and maintaining compatibility with existing circuit simulators. Another important requirement for the MOSFET model is to be generally applicable to simulation of different types of circuits and a wide range of device geometries.
The present invention overcomes the limitations of prior art by providing a method for modeling submicron MOSFETs, capable of accurately predicting performance of a MOSFET with complex geometry closely approximating the actual geometry of a device manufactured as part of an integrated circuit. At the same time it provides a sub-circuit representation of a MOSFET that is equivalent to a regular MOSFET circuit model when ideal rectangular device geometry is assumed. Advantageously, the models created using the disclosed method are compatible with standard circuit simulators. The method may be readily implemented as part of a SPICE or other circuit simulation in a design flow. Such simulation may be employed to analyze circuits comprising analog and digital designs, and to study both nominal and statistical circuit performance as well as interaction between circuit and physical design and manufacturing process. This method readily lends itself to be implemented as a part of Design For Manufacturability (DFM) flow.
The present invention consists of a method for MOSFET modeling comprising:
The present invention provides flexibility in the choice of simulation tools and simulation flow such that any SPICE-compatible or other circuit simulator can be used for subsequent simulations using MOSFET sub-circuit models created by present invention. Additionally there is no limitation as to which device-models can be used by the circuit simulator since the disclosed method makes no explicit assumption about the specific type of the MOSFET models used for each sub-circuit element. Further, the original structure and hierarchy of the SPICE model may also be maintained, allowing drop-in integration of the present invention in a design flow.
Design layout 102 can be presented in any standard format such as GDS-II.
Process information 103 is a complete set of parameters characterizing the photolithography process which may include light source parameters such as wavelength and partial coherence, stepper parameters such as numerical aperture, aberrations and misalignment, as well as photoresist development and etch process parameters. Exact number of parameters characterizing lithographic process varies depending on the specifics of the lithographic process itself and models used to simulate the process.
Step 104 extracts transistor geometry. Transistors are identified using original layout 102 (
Step 105 performs transistor partitioning. In this step cutlines are placed across the nonrectangular transistor gates to measure transistor gate linear dimension.
Step 106 performs indexing of transistor slices. There are 3 parameters (indexes) associated with each cutline: length L, width W and distance from the transistor edge Z. Parameters L and Z are directly measured while parameter W is calculated based on the distance between edge cutlines such as 403 and 407, the total number of cutlines and cutline location.
For example, if uniform partitioning is used in step 105 and Wtot is the distance between cutlines 403 and 407, then the value of parameter W associated with cutlines 404, 405 and 406 would be Wtot/4 and the value of parameter W associated with cutlines 403 and 407 would be Wtot/8. If non-uniform partitioning is used in step 105, W parameter values assigned to transistor slices change accordingly.
Step 107 generates a sub-circuit for each transistor based on the number of cutlines created and cutline parameters calculated in step 106.
Each transistor in the input netlist is replaced by a sub-circuit in the output netlist, in particular MOSFET mn1 in the original netlist is replaced by a sub-circuit consisting of 5 MOSFET devices mn1s0 through mn1s4 as shown in Table 2.
Step 110 generates updated transistor models 112 required by the updated netlist 109. Values of the parameters of the original transistor models 111 are transformed based on the L, W and Z values calculated for each transistor in step 106 and saved in the updated netlist 109. The new set of parameter values for MOSFET models is generated in such a way that new sub-circuit representation 502 of the original MOSFET 501 is electrically equivalent to the original MOSFET model when ideal geometry is assumed. Table 3 and Table 4 illustrate this process. Table 3 shows original BSIM3 model parameters and Table 4 shows updated set of model parameters generated by the method of this invention.
Optionally, to account for narrow width effects, parameters of the new output MOSFET models corresponding to different cutlines may be adjusted based on the value of parameter Z (distance from transistor edge). Required data describing MOSFET parameters on transistor width, may be obtained from either experimental or simulation-based narrow width characterization.
As described, the present invention provides a convenient method that allows for accurate prediction of performance of a MOSFET with complex geometry closely approximating the actual geometry of a device manufactured as part of an integrated circuit. Models created using the disclosed method are compatible with existing circuit simulators providing great flexibility in the simulation tools that may be employed.
This patent application is claiming the benefit of a prior filed provisional application Ser. No. 60/651,695, filed on Feb. 9, 2005, entitled “System and method for improving accuracy of MOSFET models used in circuit simulation of integrated circuits”.
Number | Date | Country | |
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60651695 | Feb 2005 | US |