Method for increasing the cut-off frequency in flip-flops

Abstract

In a flip-flop comprising a control element and a holding element, in which a first current causes the control element to set a logic state and a second current causes the holding element to maintain the logic state, the cut-off frequency is increased by dimensioning the transistors of the holding element HG to be smaller than the transistors of the control element.

Description

BACKGROUND

[0001] 1. Field of the Invention

[0002] The invention relates to a method for increasing the cut-off frequency of flip-flops.

[0003] 2. Description of the Related Technology

[0004] Circuits with flip-flops are used in the digital signal processing field for storing logic states. They consist internally of a control element, which takes the logic state which is applied to its input and makes it available for evaluation at its output, and of a holding element, which maintains the state which is set. Using a clock, inter alia, so-called frequency dividers or dividing stages can be assembled from a series connection of a plurality of flip-flops. The processing of increasingly higher frequencies requires dividing stages which operate at several gigahertz, especially in the GSM, ISM wireless communication field. Because of the development to higher frequencies, the transistors which are used in the flip-flops have to meet higher requirements in terms of the cut-off frequency thereof, which must be approximately twice the maximum frequency of the divider.

[0005] The transistor production process is becoming significantly more complex and cost-intensive due to the higher frequency requirements. The cut-off frequency of an individual flip-flop circuit results from the signal propagation time within the circuit. It is essentially determined by the product of the load resistance and the capacitance at the output line of the flip-flop and, considered quite generally, can be conceived as a low pass filter. With a given load resistance, the transistors of the circuit must be able to handle a sufficiently high current, according to the value of the capacitance which is to be recharged upon a change occurring in the logic state. If this is not the case, high-current effects will occur and the cut-off frequency of the flip-flop drop drastically.

[0006] In the methods known from the prior art, for example in M. Wurzer et. al., ISSCC 2000, San Francisco, the transistors which are used in the control elements and holding elements are dimensioned to prevent high-current effects following the maximum peak current values occurring in the control elements.

[0007] The disadvantage of the previous method lies in the fact that the different electrical requirements to be met by the control element and the holding element are not taken into account and the transistor capacitances linked with the area consequently not optimised. As these have to be recharged at the output lines of the flip-flop each time there is a change in the logic state, this has an adverse influence on the cut-off frequency of the flip-flop.

SUMMARY OF THE INVENTION

[0008] The present invention seeks to provide a method which increases the cut-off frequency of flip-flops and which can at the same time be implemented easily and inexpensively.

[0009] According to a first aspect, the present invention provides a method for increasing the cut-off frequency of a flip-flop including at least one control element having at least two transistors and at least one holding element having at least two transistors, said control element setting, by means of a first current, a logic state of said flip-flop, logic sate being maintained by said holding element by means of a second current, wherein the current carrying capacity of said transistors of said control element is adapted to the value of said first current, and the current carrying capacity of said transistors of said holding element is adapted to the value of said second current.

[0010] According to a second aspect, the present invention provides a flip-flop including at least one control element having at least two transistors and at least one holding element having at least two transistors, and means supplying a first current to said control element so that it sets a logic state of the flip-flop and a second current to said holding element so that it maintains said logic state, wherein said transistors of said holding element have smaller dimensions than said transistors of said control element.

BRIEF DESCRIPTION OF THE FIGURE

[0011] A preferred embodiment of the present invention will now be explained, by way of example only. The invention is explained in the following on the basis of in connection with the drawing, in which:

[0012] FIG. 1 is a block diagram showing an embodiment of a flip-flop.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Basically the present invention provides a method fox increasing the cut-off frequency of a flip-flop which comprises at least one control element having at least two transistors and at least one holding element having at least two transistors, and the control element sets by means of a first current a logic state of the flip-flop which is maintained by the holding element by means of a second current, wherein the current carrying capacity of the transistors of the control element is adapted to the value of the first current, and the current carrying capacity of the transistors of the holding element is adapted to the value of the second current.

[0014] Methods according to embodiments of the invention relate to adapting the current carrying capacity of the transistors of a holding element in a flip flop separately from the current carrying capacity of a control element. The task of the control element is to transfer the logic state which is applied to an input to an output of the flip-flop by means of a first current.

[0015] If the logic state at the input changes, there will also be a change in the value of the first current at the output. It is of advantage if the current in this case produces via a load element a voltage drop which corresponds to the logic states. The task of the holding element is to maintain the logic state which is set by the control element by means of a second current. If the logic state at the input of the control element corresponds to the state already existing at the output, the two currents will be equal, i.e. the requirement in terms of the value of the current carrying capacity of the transistors of the control element and the transistors of the holding element will be equal in static operating mode. If the logic state changes at the input, the value of the first current must be changed by the control element. This means that the capacitances which are present at the output or the control element must be recharged by the transistors of the control element in dynamic operating mode. An additional current is required for this when compared with the static operating mode. The current carrying capacity of the transistors of the control element must therefore be greater than the current carrying capacity of the transistors of the holding element. As the value of the current carrying capacity in the transistors is proportional to the capacitance thereof, the contribution of the transistors to the capacitance at the output of the flip-flop is reduced when compared with the prior art and the cut-off frequency is increased as a result.

[0016] The required current carrying capacity is preferably calculated by means of simulation of the circuit parts before the circuit is produced. The requirements in terms of current carrying capacity are in this case implemented by dimensioning the transistors during the layout phase, preferably by means of scaling the area of the transistor types which are used for a flip-flop circuit arrangement. According to the purely static requirements, the transistors of the holding element have smaller dimensions than the transistors of the control element. As the specific transistor capacitances are proportional to the transistor area, the reduction in the transistor area results in a reduction in the capacitance with respect to the prior art. A further advantage lies in the fact that the chip area can be reduced when producing an integrated flip-flop circuit arrangement by means of a smaller transistor area.

[0017] Referring to the drawings, the task of the flip-flop circuit arrangement which is illustrated in FIG. 1 is to store the digital state which is applied to an input IN, {overscore (IN)} and make this state available at an output, OUT, {overscore (OUT)} for further processing.

[0018] For this purpose the flip-flop comprises a current source IQ, which lies between a reference potential and a clock element D. The clock element D is also connected to a control element SG and a holding element HG and comprises an input CLK and a complementary input {overscore (CLK)}. In addition to the input IN and the complementary input {overscore (IN)}, the control element SG also comprises the output OUT and the complementary output {overscore (OUT)}. Each of the two outputs OUT and {overscore (OUT)} is separately connected via a resistor R1 and a resistor R2 of a load element L to a supply potential and to a first terminal and a second terminal of the holding element HG.

[0019] In the illustrated embodiment the clock element D comprises a first transistor T1 and a second transistor T2, the emitters of which are jointly connected to the current source IQ. The base of the transistor T1 is connected to the input CLK and the base of the transistor T2 to the input {overscore (CLK)}. The collector of the transistor T1 is also connected to the two emitters of a first transistor T3 and a second transistor T4 of the control element SG. The collector of the transistor T2 is accordingly connected to the two emitters of a transistor T5 and a transistor T6 of the holding element HG. In the control element SG the base of the transistor T3 is connected to the input IN and the base of the transistor T4 to the input {overscore (IN)}, while the collector of the transistor T3 is connected to the output {overscore (OUT)} and the collector of the transistor T4 to the output OUT. In the holding element HG the base of the transistor T5 and the collector of the transistor T6 are connected to the output line OUT and the base of the transistor T6 and the collector of the transistor T5 jointly to the output line {overscore (OUT)}.

[0020] The clock element 10 forms the starting point for the functional description. This decouples the current source IQ from the control element SG and the holding element HG. If the input CLK is at “low”, the entire current will flow through the holding element HG, as the input CLK is at “high”.

[0021] The entire current accordingly flows through the control element SG while the input CLK is “high”. Because of the “high” potential at the input CLK, the control element SG becomes transparent, i.e. the respective logic state which is applied to the input IN is reproduced inverted on the output line {overscore (OUT)} through a voltage drop at the load element L. If there is a change in potential from “high” to “low” at the input CLK, the holding element HG will take the logic state which is set by the control element SG.

[0022] As the current of the current source IQ flows either entirely through one of the transistors T3 and T4 of the control element SG or through one of the transistors T5 and T6 of the holding element HG in static mode, the four transistors T3 to T6 must have the same current carrying capacity for the static mode. In contrast, a change of potential to be carried out by the transistors T3 and T4 of the control element SG at the outputs OUT and {overscore (OUT)} can only be described by means of a dynamic mode of observation. According to the change in direction of the logic state, either the transistor T3 or the transistor T4 must for this purpose recharge the respective capacitance at the output lines OUT and {overscore (OUT)}, while the transistors T5 and T6 of the holding element HG do not bring about any change and are therefore to be considered as purely static. However the geometry of the transistors T3 and T4 must therefore be enlarged in order to handle the current peaks which occur upon changing the logic state and are proportional to the value of the capacitances present at the output lines OUT and OUT. In this case the respective capacitance consists of the capacitances of the conductor tracks, the capacitance of the load resistor L, the internal junction capacitances of the transistors T3 to T6, as well as the input capacitance of the follower stage connected to the output line OUT or the output line {overscore (OUT)}. If only the transistors T3 and T4 of the control element SG are enlarged in order to fulfill the dynamic requirements, the additional contribution to the internal transistor capacitances will be reduced to half with respect to the prior art. As the signal propagation time through the flip-flop is proportional to the product of the total capacitance and the value of the load resistor L, the cut-off frequency of the flip-flop will therefore increase or, at a predetermined frequency, the current consumption of the flip-flop will decrease with respect to the prior art.

[0023] Tests carried out by the applicants produced an increase in the cut-off frequency in a flip-flop circuit in the range of 10%. In terms of dividing stages operating, for example, in the range of 5 GHz, the result is an increase in cut-off frequency of 500 MHz. Here the transistors which have a higher internal specific transistor capacitance also exhibit a greater increase in cut-off frequency.

[0024] Thus, in summary, whereas in known methods, the area of the transistors is determined in a flip-flop circuit according to the current peaks at the control elements and this area is applied to the transistors of the holding element, according to the present method the area of the transistors of the holding element is adapted to their static current load. As the static current load is smaller than the dynamic current load of the transistors of the control element, the area of the transistors of the holding element is reduced. The total capacitance, which is to be recharged by the transistors of the control element upon a change occurring in the logic state, is therefore reduced. The cut-off frequency of the flip-flop circuit is increased accordingly.

[0025] It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations.

Claims

1. A method for increasing the cut-off frequency of a flip-flop including at least one control element having at least two transistors and at least one holding element having at least two transistors, said control element setting, by means of a first current, a logic state of said flip-flop, said logic state being maintained by said holding element by means of a second current, wherein the current carrying capacity of said transistors of said control element is adapted to the value of said first current, and the current carrying capacity of said transistors of said holding element is adapted to the value of said second current.

2. A method according to claim 1, wherein said current carrying capacities of said transistors are adapted by dimensioning said transistors.

3. A method according to claim 1 or 2, wherein said transistors of said holding element have smaller dimensions than said transistors of said control element.

4. A flip-flop produced by a method according to claim 1.

5. A flip-flop including at least one control element having at least two transistors and at least one holding element having at least two transistors, and means supplying a first current to said control element so that it sets a logic state of the flip-flop and a second current to said holding element so that it maintains said logic state, wherein said transistors of said holding element have smaller dimensions than said transistors of said control element.