1. Field of the Invention
The present invention relates to computer systems. More particularly, the invention relates to a method and apparatus for segmenting and reassembling ATM data in an ATM interface.
2. Description of Related Art
Asynchronous transfer mode (ATM) is a connection-oriented cell switching technique in which cells are of a fixed length. Each cell includes a header of 5 bytes and a payload or information of 48 bytes. The header includes virtual channel information and is used in routing. The data portion may carry a variety of information types including voice, data, images, text and video. In recent years, ATM has become universally accepted as the transfer mode of choice for broadband integrated service digital networks (BISDN).
The header 104 of ATM cell 100 includes six elements including the generic flow control 112, the virtual path identifier 116, the virtual channel identifier 120, the payload type identifier 124 and a header error control 128. The header values are assigned during the connection set up and translated when switched from one section of a network to another section. In particular, the virtual path identifier (VPI) 116 and the virtual channel identifier (VCI) 120 control the routing of the cell.
Typically, in order to prepare and receive ATM data, data must undergo several layers of processing. The lowest layer, a physical layer, performs physical medium dependent functions such as bit timing functions and cell rate decoupling which inserts idle cells in a transmitting direction in order to adapt the rate of the ATM cells to the payload capacity of a transmission system and removes idle cells in the receiving direction. Above the physical layer is an ATM layer which performs header generation and extraction, cell multiplexing and demultiplexing, translation of VPI/VCI fields and generic flow control. An ATM adaptation layer above the ATM layer performs the adaption of the lower layers including the ATM layer and the physical layer to OSI higher layer protocols.
One of those layers, an ATM adaption layer function (AAL functions) is divided into two sublayers, typically, 1) a segmentation and reassembly (SAR) sublayer, and 2) a convergence (CS) sublayer. During transmission, the SAR sublayer performs segmentation of higher layer information into a size suitable for an ATM cell payload. When receiving ATM cells, the SAR sublayer reassembles the contents of the cells of a virtual connection into data units to be delivered to higher layers. The functions of the SAR sublayer are typically performed by hardware implemented in the computer such as a SAR chip. Examples of typical SAR chips are made by Integrated Device Technologies (IDT) of Santa Clara, Calif., and Motorola Corporation of Schaumburg, Ill.
Implementing the SAR in a chip has several disadvantages. A first disadvantage of implementing the SAR chip is cost. As the price points of personal computers (PCs) continue to decrease, the additional expense of SAR chips is undesirable. A second disadvantage of using SAR chips is the limited flexibility in changing other components coupled to the SAR chip. Thus, a more inexpensive and flexible method of implementing SAR functions is needed.
In one embodiment, the present invention relates to a method of performing asynchronous transfer mode segmentation functions. In one embodiment of the invention, data to be sent is received. The data is segmented to generate a plurality of ATM cells. The plurality of ATM cells is buffered in a memory device. The buffered plurality of ATM cells undergoes traffic shaping prior to transmission of the plurality ATM cells on a network.
The advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings wherein:
In the following description, a system and apparatus for providing an interface between a transmitting and receiving unit in a network transferring ATM data will be described. The system uses software implemented in a multipurpose central processing unit to form the segmentation and reassembly functions in a personal computer. The use of software to perform the segmentation and reassembly reduces the cost of building a personal computer. The description which follows will include numerous details set forth in order to provide a thorough understanding of the present invention. For example, details will include bus types and specific examples of processors. However, it will be apparent to one skilled in the art that such specific details are not required in order to practice the present invention.
In order to handle the ATM cells, a prior art SAR chip 208 including an SAR ASIC 212 coupled to a memory buffer 216 is implemented in an overall computer system 220 as illustrated in
A PCI bus controller 240 controls the flow of data along PCI bus 236. The PCI bus controller 240 receives interrupts when memory buffer 216 is full. The PDUs may be transferred to a PC memory 244 from PCI bus 236 and subsequently to a CPU 248 for processing.
The architecture illustrated in
When outputting data, the CPU continues to generate new data which is associated with header information to form ATM cells and transferred along route 366 to PCI bus interface 358. The ATM cells are stored in a section of FIFO 354 for eventual transfer along egress route 370 to UTOPIA bus interface 348 for output to the network.
When receiving AAL protocol PDUs, segmentation block 416 receives a stream of AAL protocol PDUs 420 destined for one or more ATM VCs and segments them into ATM cells. A traffic shaping block 424 receives the stream of ATM cells from the segmentation block 416 and outputs a stream of ATM cells for transmission to meet the quality of service (QOS) requirements for each VC and for the entire link.
In block 520, the CPU determines whether the current cell still has remaining space in the information or payload section of the ATM cell. When the information section of a cell is completely full, the CPU writes the cell header for a new ATM cell in block 524. When the information section of the current cell is not full, the CPU continues to copy cell payload data from the input buffer to the information section of the cell in block 528. In block 532, the CPU computes a new partial cyclic redundancy check (CRC) used to protect against bit errors over the cell payload.
When in decision block 536, the CPU determines that the input buffer is empty, the system goes to decision block 512 to determine whether there are additional input buffers left in the packet. In decision block 512, when it is determined that no more data remains in the packet for transfer to a cell, the system determines whether the information section of the current cell being processed has at least 8 bytes open in block 540. When the current cell does not have at least 8 bytes open, the system pads the remainder of the current cell in block 544 and generates an additional cell filled with padding except for the last 8 bytes in block 548. When open space left in the current cell exceeds 8 bytes, the open space, except for the last 8 bytes, is filled with padding data in block 552. After padding the cell in either block 552 or block 548, the final 8 bytes of the cell are filled with trailer data including, in one embodiment, CPS-UUCPI and AAL5 PDU length in block 556. The final CRC is also computed and inserted into the final 4 bytes of the trailer in block 560. In block 564 the buffer of ATM cells is delivered for traffic shaping.
A traffic shaper processes the buffer of ATM cells to direct traffic on a hardware network.
In one embodiment of the invention, the soft SAR is also used to receive data from hardware at a processing unit. The procedure for receiving such data is illustrated in the flow diagram 700 of
When the cell contains an end of PDU signal in block 728 indicating that the cell is the last cell in a data sequence, the CPU determines whether a CRC matches in block 732. When no CRC match is found an error occurred during data transfer and a portion of a payload data unit (PDU) received so far is dropped in block 734, the system returns to block 708 to determine a number of retrieved cells remaining in the input buffer in block 708. When a CRC match is found in block 732, the CPU determines whether there is a length match in block 736. When the length of the payload data unit does not match the indication for the expected length an error has occurred and the PDU is dropped in block 740. The system returns to determine a number of retrieved cells remaining in the input buffer in block 708.
When in block 730 the lengths match, the system transfers the PDU to a virtual channel (VC) owner in block 744. In alternate embodiments, the PDU may also be transmitted to an AAL user in block 752. Thus, the software of the system receives the ATM cells and reassembles the data packets transferring only PDUs to the VC owner or to the appropriate AAL user. The process continues until no cells are found in the input buffer of block 708 in which case the system has completed in data transfer block 756.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.
Number | Date | Country | |
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Parent | 09263918 | Mar 1999 | US |
Child | 11167714 | Jun 2005 | US |