BACKGROUND OF THE INVENTION
There are several methods currently used to develop feedback in an amplifier. One technique is to use a differential pair to accommodate negative feedback by using one side of the differential pair for a single-ended input and the other as a feedback path. This can be accomplished directly, as illustrated by U.S. Pat Nos. #4,107,619, #4,188,588 and #5,260,672, or more abstractly in high gain amplifiers vis-a-vis well known operational amplifier feedback methods. Both of these methods require numerous active devices in the form of current sources, current mirrors, gain stages, and the initial differential pair itself In addition to the employment of numerous active devices, high gain amplifiers used in the manner of operational amplifiers suffer the problem of relatively low input resistance and relatively high feedback resistance.
BRIEF SUMMARY OF THE INVENTION
The present invention depicts a method of configuring FET-based amplifiers in a current balancing circuit that allows for two direct gate inputs demonstrating arbitrary shunted input resistance and low series gate resistance. Used in a circuit with an output signal that is out of phase with the input, negative feedback can be introduced into the circuit while utilizing minimal active circuit components and simultaneously raising the input impedance and decreasing the feedback path impedance. The realization of this invention is an amplifier with decreased distortion and lowered output impedance with improved frequency performance.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1: Illustration of invention using N-channel MOSFETs with a constant current source.
FIG. 2: Illustration of invention using N-channel JFETs with a constant current source.
FIG. 3: Illustration of invention using P-channel MOSFETs with a constant current source.
FIG. 4: Illustration of invention using P-channel JFETs with a constant current source.
FIG. 5: Illustration of the invention using N-channel MOSFETs in a cascode configuration with a constant current source.
FIG. 6: Illustration of the invention in a differential application using N-channel MOSFETs in a cascode configuration with constant current sources.
DETAILED DESCRIPTION OF THE INVENTION
The topology of the amplifier depicted in FIG. 1 comprises a symmetrical arrangement of similar N-channel MOSFETs Q11 and Q12. A constant current source K1, fed by power supply +V1, produces a current I10 that is divided as evenly as is practical in the quiescent state between the two N-channel MOSFETs Q11 and Q12 at node N1, resulting in channel currents I11 and I12, respectively. It should be appreciated by those trained in the art that, while the invention is demonstrated by way of example using active, constant current sources, effects consistent with the spirit of the present invention can be achieved with constant voltage sources. Source resistors R11 and R12 have an induced voltage I11R11 and I12R12 that biases Q11 and Q12, respectively, resulting in, effectively, a two transistor degenerated amplifier with resistors R11 and R12 terminating in power supply −V1. R11 and R12 are typically similar in value, though gate-source offset variations in Q11 and Q12 can be accommodated with small relative changes in the values of R11 and R12. R11 and R12 may be omitted depending on the operating characteristics of transistors Q11 and Q12. The gate of Q11 is connected to a bias voltage Vbias1 by an input resistor R10, where Vbias1 is a common reference point for the input Vin1 and the output Vout1. Given the high impedance of the gate of Q11, R10 is effectively the input impedance experienced by the source Vin1.
Capacitor C1 provides quiescent DC immunity from the voltage at node N1 to the resistor divider network comprised of resistors R13 and R14. Those trained in the art will observe that, notwithstanding the effects of transistor Q12, the amplifier comprising constant current source K1 and transistor Q11 will create an amplified, out of phase signal at terminal Vout1. The gate of transistor Q12 is driven out of phase from the input the magnitude of which is selectable by the values of resistors R13 and R14. Negative feedback is injected at the gate of Q12, manifesting as negative feedback in the cumulative current I11+I12 and the resultant voltage at node N1.
Signal variations driven by input Vin1 manifest as output Vout1, as node N1 observes deviations between constant current I10 and cumulative transistor current I11+I12. This results in a change in the voltage at node N1 and induces output voltage Vout1 across the total load resistance, which is R13+R14 in parallel with any external load resistance. The series resistance of R13 and R14 is chosen to reflect minimal change of the total load resistance when the external load is applied while simultaneously being as low in value as possible to reduce the deleterious effects of the gate capacitance of Q12. The value of C1 at frequencies of interest must be chosen such that the reactance of C1 is small compared with the total load resistance.
It should be noted that the feedback network formed by decoupling capacitor C1 and resistors R13 and R14 is not specific to the present invention. Any feedback network, passive or active, accomplishing the objective of introducing an out of phase signal at the gate of Q12 originating at node N1 that is consistent with the DC operating parameters of the amplifier given specific choices of power supplies +V1 and −V1, currents I10, I11 and I12, source resistors R11 and R12, gate bias voltage Vbias1, and transistor types Q11 and Q12, accomplishes the claims of the present invention. The network shown, being versatile with respect to application, is a preferred embodiment of the use of the invention in a practical circuit.
FIG. 2 depicts a claimed topology of the present invention that is identical except for transistors Q21 and Q22 being replaced by N-channel JFETs. FIG. 3 depicts a claimed topology involving P-channel MOSFETs Q31 and Q32. In this illustration it should be noted that, relative to the similarly drawn circuits previously presented, power supplies +V3 and −V3 are reversed. Furthermore, the active constant current source K3 induces a current I30 that is reverse the complimentary topology. FIG. 4 depicts the present invention using P-channel JFETs Q41 and Q42.
The amplifier is further improved in FIG. 5 with the addition of a cascode stage comprising transistor Q53 and associated gate bias voltage Vref5. As a result, capacitor C5 decouples the drain of Q53 rather than node N5. Those trained in the art will recognize the enhanced benefit of this arrangement vis-a-vis improving frequency performance by decreasing the effective gate capacitance of transistors Q51 and Q52. While improved with respect to the mitigation of effective gate capacitance, this amplifier experiences the same relationship between values of external load resistance and capacitor C5 with respect to frequency performance.
The amplifier is made differential as illustrated in FIG. 6 by combining two symmetrical copies of the amplifier depicted in FIG. 5. In this case the two halves of the resulting differential amplifier are identified by diagram suffixes a and b. The two halves of the amplifier are driven by inputs Vin6a and Vin6b with signals that are out of phase with each other with respect to bias voltage Vbias6. This results in a differential signal output exhibiting voltages Vout6a and Vout6b, respectively. The symmetrical arrangement of the differential amplifier allows the position of output decoupling capacitors C6a and C6b to be altered such that the external load resistance is connected directly between terminal Vout6a and Vout6b. Cascode transistor gate reference voltages Vref6a and Vref6b can be adjusted to null the quiescent voltage differential between Vout6a and Vout6b. Since series resistance R63a+R64a (as well as R63b+R64b) is designed to be large compared to the external load resistance between terminals Vout6a and Vout6b, the values of C6a and C6b can be decreased from that of the non-differential variations of the invention while maintaining similar frequency performance. It is only the feedback to transistors Q62a and Q62b that is effected by this change in topology (compared to that of transistor Q52, FIG. 5, for example).
As with the amplifier topology depicted in FIG. 1, the amplifier topologies depicted in FIG. 5 and FIG. 6 are amenable to the transistor type alternatives presented in FIG. 2, FIG. 3 and FIG. 4 (namely N-channel JFETs, P-channel MOSFETs and P-channel JFETs). FIG. 5 and FIG. 6 are illustrated as exemplars of these alternatives while abiding the spirit of the present invention.
Patent Application
20120313705
