1. Field of the Invention
The present invention relates to the field of error correction codes such as the ones employed for wireline and wireless digital communication systems and in data storage systems. As an example, the present invention relates to iterative decoding methods that implement the Maximum A Posteriori (MAP) Algorithm.
2. Description of the Related Art
A digital communication system of both wireless and wireline type usually comprises a transmitter, a communication channel and a receiver as known by those skilled in the art.
The communication channel of such system is often noisy and introduces errors in the information being transmitted such that the information received at the receiver is different from the information transmitted.
In general, in order to correct an error of the channel transmitted through wireline and wireless environments, the digital communication system uses a protection method by which the transmitter performs a coding operation using an error correction code and the receiver corrects the error produced by the noisy channel.
Various coding schemes have been proposed and developed for performing correction of errors introduced by the channel. In particular, turbo codes (which are Forward Error Correction codes, FEC) are capable of achieving better error performance than conventional codes. Furthermore, turbo codes can achieve exceptionally low error rates in a low signal-to-noise ratio environment.
For this reason, such turbo codes can usefully be employed in wireless communications, for example in the more recent CDMA wireless communication standard.
A detailed description of turbo coding and decoding schemes can be found in “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-codes”, Berrou et al., Proc., IEEE Int'l Conf. On communications, Geneva, Switzerland, 1993, pp. 1064-1070. Particularly, turbo codes are the parallel concatenation of two or more recursive systematic convolutional codes separated by interleavers.
As known by those skilled in the art, decoding of turbo codes is often complex and involves a large amount of complex computations. Turbo decoding is typically based on a Maximum A Posteriori (MAP) algorithm which operates by calculating the maximum a posteriori probabilities for the data encoded by each constituent code.
While it has been recognized that the MAP algorithm is the optimal decoding algorithm for turbo codes, it is also recognized that implementation of the MAP decoding algorithm is very difficult in practice because of its computational complexities.
To reduce such complexities, approximations and modifications to the MAP algorithm have been developed. These include a Max-Log-MAP algorithm and a Log-MAP algorithm. The Max-Log-MAP and Log-MAP algorithms are described in detail in “A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain”, Robertson et al., IEEE Int'l Conf. on Communications (Seattle, Wash.), June, 1995.
To reduce the computational complexity of the MAP algorithm, the Max-Log-MAP and Log-MAP algorithms perform the entire decoding operation in the logarithmic domain. In fact, in the log domain, multiplication operations become addition operations, thus simplifying numeric computations involving multiplication.
The object of the present invention is to provide an improved method for performing iterative decoding of information which has been coded in accordance with error correction codes such as, for example, a turbo code.
Particularly the inventive method comprises:
In accordance with another object, the present invention relates with a receiving apparatus comprising a decoder for performing in a communication system iterative decoding of information coded by an error correction code, the decoder comprising:
The characteristics and the advantages of the present invention will be understood from the following detailed description of exemplary non-limiting embodiments thereof with reference to the annexed Figures, in which:
Particularly, the communication system 100 comprises a transmitter 101, a communication channel 102 and a receiver apparatus 103. The transmitter 101 comprises a source 104 of digital data and an encoder 105 to encode data in accordance with error correction codes in order to make the transmission more robust against errors introduced by the channel 102. Furthermore, the transmitter 101 comprises a modulator 106 to translate the encoded bits into signals suitable to be transmitted through the channel 102.
Instead, the receiver apparatus 103 comprises a demodulator 108 for translating the received signals into bit likelihoods or soft values indicating with which probability a received bit is a 0 or 1 logic. Subsequently, such soft values are elaborated by a decoder 109 that retrieves the source bits.
In order to avoid errors introduced by the noisy channel 102, the data bits to be transmitted can be, advantageously, encoded using a PCCC (Parallel Concatenated Convolutional Coding) turbo code known in the art.
Particularly, employing the PCCC turbo code in the digital communication system 100, data bits to be transmitted over the communication channel 102 are encoded as an information sequence (also called systematic information) and two or more parity sequences (also called parity information).
Particularly, such encoder 200 comprises a first 201 and a second 202 encoder, for example, substantially equal each other. The encoders 201 and 202 are chosen among the recursive systematic convolutional codes (RSC) and are described in “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-codes”, Berrou et al., Proc., IEEE Int'l Conf. On communications, Geneva, Switzerland, 1993, pp. 1064-1070 and in U.S. Pat. No. 6,298,463 B1 (Bingeman et al.), herein incorporated by reference.
With reference to a first information bit sequence dk which corresponds to the data to be transmitted, the PCCC encoder 200 generates a systematic sequence of bits Xk, a first parity sequence Y1k and a second parity sequence Y2k.
As shown in
On the contrary, a second information bit sequence dk1 corresponds to the first information bit sequence dk after elaboration made by an interleaver 203. Such second information bit sequence dk1 represents the input of the second encoder 202 which produces the second parity sequence Y2k at its output.
The interleaver 203 in the PCCC turbo code encoder 200 operates, as it is known, to interleave the information bits supplied to the same encoder 200. Such interleaving operation can be accomplished, for example, storing all input information bits consecutively in the rows of a matrix of storage locations and then reading consecutively the columns of the same matrix to access the stored bits (row-column interleaver).
It should be observed that, typically, in the PCCC encoder 200, the interleaver 203 is embedded into the encoder structure to form an overall concatenated code. In more detail, the interleaver 203 is employed to decorrelate the decoding errors produced in the first convolutional code (i.e. the first encoder 201) from those coming from the second convolutional code (i.e. the second encoder 202).
The systematic sequence of bits Xk, the first Y1k and second Y2k parity sequences produced by the PCCC encoder 200 are then multiplexed to form a code word. After encoding, the code word is modulated according to techniques known in the art and transmitted over the noisy communication channel 102, either wired or wireless.
In more detail, such decoder 300 comprises a first 301 and a second 302 decoder for receiving and decoding the soft values xk, y1k and y2k produced by the demodulator 108 of the receiver apparatus 103. Such soft values xk, y1k and y2k correspond to the systematic bit Xk, the first parity bit Y1k and the second parity bit Y2k, respectively, which have been demodulated and then filtered and sampled by, for example, a suitable filter/match/sample unit not shown in
Furthermore, the PCCC turbo decoder 300 may comprise a computation unit and a memory unit both not shown in
Moreover, the PCCC turbo decoder 300 can be constructed as an application specific integrated circuit (ASIC) or mapped on a field-programmable gate-array (FPGA) or a digital signal processor (DSP) software or using other suitable technologies known by one skilled in the art.
As can be seen, the soft values xk and y1k corresponding to the systematic bit Xk and the first parity bit Y1k, represent the inputs of the first decoder 301. The output of the first decoder 301 is a first log-likelihood ratio Λ1e(dk) to be sent to the second decoder 302 through a first interleaver 303. Such first interleaver 303 is analogous to the interleaver 203 of the PCCC encoder 200.
Moreover, a first interleaved log-likelihood ratio Λ1e(dk1) represents a first input of the second decoder 302 and the soft value y2k corresponding to the second parity bit Y2k represent a second input for the same decoder 302.
Furthermore, a second interleaved log-likelihood ratio Λ2e(dk1) produced at the output of the second decoder 302 represents the input of a deinterleaver 304 in order to generate a deinterleaved log-likelihood ratio Λ2e(dk) to be sent to the first decoder 301 as a feedback signal.
As known by those skilled in the art, the log-likelihood ratios Λ1e(dk) and Λ2e(dk1) produced at the output of the first 301 and second 302 decoders are the so called “extrinsic information”. Such extrinsic information Λ1e(dk), Λ2e(dk1) each one feeding the successive decoder in an iterative fashion is used as an estimation of the “a priori probability” of the logic value (0 or 1) of information bits. The first interleaver 303 and the deinterleaver 304 reorder the extrinsic information Λ1e(dk) and Λ2e(dk1), respectively, before each exchange between the first 301 and second 302 decoders.
The reliability of the estimation increases for each iterative decoding step. Finally, a hard decision on the information bits is taken at the end of the last iteration. Particularly, at the last step of iteration, a further deinterleaver 304′ deinterleaves the second log-likelihood ratio Λ2e(dk1) produced by the second decoder 302 and the decoded bits are provided at the output of a threshold circuit 305.
According to the described example, the first 301 and second 302 modules are identical for the PCCC Turbo decoder. They can operate using different algorithms of the type Maximum A Posteriori (MAP).
An example, the first 301 and second 302 decoders implement a MAP algorithm, such as the one proposed by Bahl et al in “Optimal Decoding Of Linear Of Linear Codes For Minimizing Symbol Error Rate”, IEEE Trans. Inform. Theory, vol. IT-20, pp. 248-287, March 1974, herein incorporated by reference.
Particularly, the first 301 and the second 302 decoders can employ the MAP algorithms in the forms “Log-MAP” and “Max-Log-MAP” algorithms, which are described in “A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain”, Robertson et al., IEEE Int'l Conf. on Communications (Seattle, Wash.), June, 1995, herein incorporated by reference.
More particularly, as it will be described hereinafter, the first decoder 301 can perform at least one calculation in accordance with the “Log-MAP” algorithm.
Preferably, the modules of the architecture shown in
Following, an example of the inventive decoding method provided by the PCCC turbo decoder 300 will be described. As already stated, such turbo decoder 300 operates, at least in part, in accordance with the Log-MAP algorithm.
Further details on the mathematical bases of the inventive method can be found in the above mentioned paper “Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-codes”, Berrou et al., Proc., IEEE Int'l Conf. On communications, Geneva, Switzerland, 1993, pp. 1064-1070.
Particularly, the first decoder 301 computes the A Posteriori Probability in logarithmic domain. The output of such decoder 301, i.e. the first log-likelihood ratio Λ1(dk), can be expressed as:
where m and m′ are the trellis states (known to the skilled person) at time k and k−1, respectively. Moreover, values α, β are usually called forward, and backward metrics and γ is usually called branch transition probability. These three quantities are kind of probabilities computed on the basis of the following equations:
where hα and hβ are normalization constants.
Moreover, Rk corresponds to the soft values xk, y1k at the output of the noisy channel 102 after demodulation. With p( ) is indicated the transition probability of a discrete gaussian memoryless channel. Then, q( ) is the function that select the possible transition in a convolutional encoder finite state machine and π( ) is the transition state probability.
As known by those skilled in the art, the values α and β can be recursively calculated from γ during the trellis forward and backward recursions, respectively.
If we apply the logarithm operator to the branch transition probability γ, we obtain a further branch transition probability {circumflex over (γ)} expressed as:
{circumflex over (γ)}(Rk,m′,m)i=log γ(i(Rk,m′,m))=log [p(Rk/dk=i,Sk=m,Sk−1=m′)q(dk=i/Sk=m,Sk−1=m′)]+log(π(Sk=m/Sk−1=m′)) (5)
then, the forward α and backward β metrics can be expressed as further forward {circumflex over (α)} and backward {circumflex over (β)} metrics:
where the terms Hα and Hβ correspond to the above indicated normalization constants hα and hβ and the first log-likelihood ratio Λ1(dk), can be expressed as:
It should be observed that the quantities in (6), (7) and (8) can be computed by solving recursively terms such as the following:
log(exp(α1+α2))=max(α1,α2)+log(1+e−|α
where the operator max*(a1,a2) comprises a max operator between general quantities a1 and a2 and a correcting factor log(1+e−|a
As an example, the recursion to compute the metrics {circumflex over (α)} will be performed by a recursive application of Eq (9) where the arguments will be terms like:
{circumflex over (γ)}i(Rk,m′,m)+{circumflex over (α)}k−1j(m′).
Instead, the computation of Λ will be performed by a two recursive application of Eq (9) (one for each term of the subtraction of expression (8)) where the arguments will be terms like:
({circumflex over (γ)}1(Rk,m′,m)+{circumflex over (α)}k−1j(m′)+{circumflex over (β)}k(m)).
Advantageously, to approximate the correcting factor log(1+e−|a
Such LUT could be memorized in the memory 500 provided in the decoder 300 and, for example, it can be generated by a processor external to the turbo decoder 300 and downloaded into the decoder itself during data processing of the input data. Alternatively, the LUT can be generated within the turbo decoder 300.
It should be observed that the number of elements of the LUT depends on the metric representation precision.
Accordingly, we assume that the branch transition probabilities {circumflex over (γ)} are digitized according to the formula:
{circumflex over (γ)}q=round({circumflex over (γ)}2p) (10)
where p is the number of bits dedicated to the precision or equivalently 2−p is the quantization interval.
Then, assuming that a saturation is applied and considering that a limited number of bits is available in any real implementation:
where d is the number of bits dedicated to the signal dynamic and p+d is equal to the number of ADC bits as known by those skilled in the art.
Consequently, each element in the LUT can be defined as:
LUT(Δ)=round(log(1+exp(−Δ/2p))2p) (12)
where Δ=|{circumflex over (γ)}q1−{circumflex over (γ)}q2| and the round operator represents the nearest integer. Each value LUT(Δ) represents the correcting factor of the max*(a1,a2) operator expressed by the formula (9).
Generally, the LUT has a limited number of elements given by the maximum integer Δmax that satisfies the following inequality:
log(1+exp(−Δmax/2p))≧2−(p+1) (13)
For example, the LUT obtainable the levels of precision p=1 is shown in
The argument Δ of the LUT can varies within a limited range having Δmax=4 as maximum limit. Each tabled value is associated to a corresponding value of the argument Δ.
The following Table 2 shows the tabled values of the LUTs for the level of precision p=2 and p=3. The values of the argument Δ are not shown in Table 2 for seek of clarity.
Neglecting the correcting factor log(1+e−|a
In the description below the LUT corresponding to the equation (12) will be called standard LUT, “Std LUT”.
Moreover, a method of using the Std LUT will be now described with reference to
Step 10: initial step “Init”;
Step 11: computing Δ=({circumflex over (γ)}1−{circumflex over (γ)}2);
Step 12: computing |Δ|;
Step 13: performing the conditional procedure:
if Δ≦Δmax (step block 13 of
Step 16: end of the method.
It has to be noticed that the standard look-up tables Std LUTs have size reduced at minimum, but the standard approach requires the computation of the modulus and a check on its value. These operations that have to be performed in a recursive manner require great computational power.
In view of the above, a look-up table alternative to the standard one STd LUT and a method of using the table alternative to the standard approach, are proposed, in accordance with one embodiment of the invention. Particularly, in the memory 500 is memorized a look-up table “Ext LUT” 600 still derivable from equation (12) but different from the Sdt LUT discussed above.
In detail, such Ext LUT 600 is such that:
the number of tabled values, N, is equal to twice than the maximum expected metric difference ΔM plus one : N=2ΔM+1;
the LUT is filled with values equal to zeros (that is to say, null values) except in the positions;
i=ΔM+1+k with k=0:Δmax where Ext LUT(i)=Std LUT(k+1);
i=ΔM−k with k=1:Δmax where Ext LUT(i)=Std LUT(k); and
the maximum expected metric difference ΔM can be estimated on the basis of the particular turbo code employed.
In other words, the look-up table Ext LUT 600 includes:
Therefore, the Ext LUT shows an “extended size” in comparison with standard LUT, Std LUT.
Table 4 shows three examples of extended look-up tables Ext LUT 600, for different precisions p.
Each of the tabled values is associated to the index i above defined.
The max*( ) algorithm implemented by the first decoder 301 is:
max*({circumflex over (γ)}1,{circumflex over (γ)}2)=max({circumflex over (γ)}1,{circumflex over (γ)}2)+LUT(ΔM+1+{circumflex over (γ)}1−{circumflex over (γ)}2) (14).
In accordance with an example of the invention, the processor module 400 of the first decoder 301 uses the look-up table Ext LUT 600 as schematically shown in
Step 1: start “Init”;
Step 2: the first computing module 401 computes the current index i by summing said first argument, said maximum limit and the value one:
i=Δ+ΔM+1;
Step 3: on the basis of the computed index i the retrieving module 403 reads the look-up table Ext LUT 600 from the memory 500, and retrieves a corresponding tabled value;
Step 4: end of the procedure.
Therefore, by means of the Step 3, the processor module 400 obtains the corrective factor of equation (14) that can be zero or different from zero. It has to be observed that the procedure described with reference to
According to the example described, the computing module 401 computes the transition probabilities {circumflex over (γ)} and computes the Forward {circumflex over (α)}, the Backward {circumflex over (β)} metrics and the Log-Likelihoods Ratio Δ1(dk) in accordance with the equations (6), (7) and (8).
As an example,
In
Another branch of the architecture 700 shows the operations performed to compute the index i and the use of the Ext LUT 600 in such a way to obtain the correcting factor of the max algorithm. The correcting factor is then added, by means of a corresponding node, to the max term. The backward metrics {circumflex over (β)} are computed in an analogous way.
Moreover,
On the basis of the systematic bit X and the first parity bit Y1 and on the basis of a value of a Log-Likelihoods Ratio Λ1, evaluated in a previous recursion step, a computing module 801 gives the transition probabilities {circumflex over (γ)} which is stored in a corresponding first memory module 802.
The architecture 800 includes recursion modules 700, 701, 702 and 703 for computing, respectively, the Forward metrics {circumflex over (α)}, the Backward metrics {circumflex over (β)} and the first and second terms Λ—1−Λ—2 of the expression (8).
The recursion module 700 has been already described with reference to
With reference to the evaluation of the quantities of the equations (6), (7) and (8), in accordance with an example of the invention the architectures 700 and 800 can be configured so as to evaluate all these three quantities by applying for each of them the Log-MAP algorithm using the look-up table Ext LUT 600.
According to an alternative embodiment, the Log-MAP algorithm can be applied to only one or two of the above quantity, while the remaining one is computed by means of the Max-Log-Map algorithm. The applicant has made a profiling test with a proprietary VLIW (very long instruction word) digital signal processor. In this test the complexity of the decoding process using a look-up table in accordance with the invention (Ext LUT) is compared with the complexity of the decoding process using the standard look-up table and the decoding process using the Max-Log MAP algorithm.
Table 5 shows the results of the test reporting the complexity increase with respect to Max-Log-MAP algorithm. The test reports the case of PCCC with 8 decoding iterations and the complexity is measured in terms of clock cycles required by the decoding processes.
The adoption of Ext LUT reduces the amount of clock cycles more than 50% compared to the Std LUT case. The implementation of Log-MAP algorithm in software, using the Std LUT, costs 5 times more than Max-Log-MAP in term of complexity; the cost becomes approximately two time with same performances at the expense of a certain amount of extra memory. However, in practical cases, Ext LUT size is not very large and the advantage in term of complexity/speed is often a good reason to accept the extra amount of memory.
The gain, obtained using Ext LUT, is due to the fact that a software implementation becomes extremely inefficient when operations are “interrupted” by conditional expression. Specifically, for VLIW machines, like the one used for the complexity estimation presented in, the pipeline must be discharged due to a branch operation: this fact justifies the large difference between the two cases.
No performance loss is paid with the adoption of Ext LUT because Std and Ext LUTs are perfectly equivalent in terms of signal processing.
Also in hardware implementation the present invention allows a complexity reduction in the management of max* operator. As shown in
Even if the above description refers to the case in which the teachings of the invention are implemented only by the first decoder 301, it has to be pointed out that such teachings can be applied alternatively or, preferably, in addition also to the second decoder 302. Advantageously, the second decoder 302 is so as to compute quantities analogous to the above described probabilities α, β and computes the likelihood-ratio Λ2 in accordance with the method above described with reference to the first decoder 301. To this end, a further look-up table, analogous to the table 600, can be stored in the decoder 300 and employed by the second decoder 302 or alternatively, the second decoder can employ the same look-up table 600 of the first decoder 301. The processing performed by the second decoder 302 is analogous to the one described with reference to the architectures 700 and 800 shown in
Moreover, it has to be noticed that the teachings of the present invention can be applied also to codes different from the turbo code. An example of another code, for which the extended look-up table (including values equal to zero) can be used, is described in the paper of Hagenauer J.; Offer E.; Papke L.: “Iterative Decoding of Binary Block and Convolutional Codes” IEEE Trans. Inform. Theory, March 1996, pp. 429-445, herein incorporated by reference.
In accordance with the authors of the above paper, the Log-Likelihoods Ratio LLR of the sum of two binary variables a,b with LLR La, Lb is given by:
The LLR of the sum of more than two binary variables is given by the recursive application of the equation (15). This formula can be exploited to decode every linear binary block code. It is worth to note that:
Another code to which the present invention can be applied is the Low-Density Parity Check Codes (LDPCC) proposed by Gallager R. G. in “Low-Density Parity-Check Codes”, IRE Trans. Information Theory, pop. 22-28, January 1962. The LDPCCs are an important class of codes decodable through the application of the above formulas (16). An interesting application of the above formulas to the decoding of LDPCC can be found in the paper of X. Hu, E. Eleftheriou, D.-M. Arnold and A. Dholakia. “Efficient Implementations of the Sum-Product Algorithm for Decoding LDPC Codes”. In Proc. IEEE Globecom, 2001.
As clear from the above, the present invention shows important advantages:
Obviously, to the decoding method of the present invention, those skilled in the art, aiming at satisfying contingent and specific requirements, may carry out further modifications and variations, all however being contemplated within the scope of protection of the invention, such as defined in the annexed claims.
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6298463 | Bingeman et al. | Oct 2001 | B1 |
7246295 | Xu | Jul 2007 | B2 |
20030056167 | Yuan et al. | Mar 2003 | A1 |
20030091129 | Zhang et al. | May 2003 | A1 |
20050052991 | Kadous | Mar 2005 | A1 |
Number | Date | Country | |
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20070157066 A1 | Jul 2007 | US |