Claims
- 1. A method for manufacturing a semiconductor device, comprising the steps of:
- forming a semiconductor substrate of a first conductivity type having a first impurity region and a second impurity region of a second conductivity type;
- forming an oxide film on said semiconductor substrate;
- forming on said oxide film a silicon nitride film having a first opening above said first impurity region and a second opening above said second impurity region;
- forming a contact hole in said oxide film through said second opening;
- forming a conductive layer containing an impurity of the first conductivity type, and made of a material selected from the group consisting of polycrystalline silicon and metal silicide, on said silicon nitride film and exposed regions of said oxide film and said substrate;
- selectivity removing said conductive layer to leave a first portion on said oxide film and a second portion on said substrate, said first portion acting as a barrier layer for protecting said oxide film, and said second portion acting as an intermediate layer;
- forming a third impurity region of the first conductivity type in said second impurity region by diffusing the impurity of said second portion into said second impurity region; and
- forming metal electrodes connected to said barrier layer and said intermediate layer.
- 2. A method according to claim 1, wherein said conductive layer has a thickness of 500 to 5,000 .ANG..
Priority Claims (1)
Number |
Date |
Country |
Kind |
56-43697 |
Mar 1981 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 668,188, filed Nov. 5, 1984 now abandoned which in turn is a continuation of Ser. No. 361,091, filed Mar. 23, 1982, now abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (5)
Number |
Date |
Country |
0031450 |
Aug 1981 |
EPX |
2083346 |
Dec 1971 |
FRX |
53-36485 |
Apr 1978 |
JPX |
55-86148 |
Jun 1980 |
JPX |
2019091 |
Oct 1979 |
GBX |
Non-Patent Literature Citations (2)
Entry |
Ridout, "Methods of Fabricating MOSFET Integrated Circuit with Low Resistivity Interconnection Lines", IBM Tech. Disc. Bull., vol. 23, No. 6, Nov. 1980, pp. 2563-2566. |
Dodds et al., "Error Tolerant Adaptive Algorithms for Delta Coding", Conference Record of the 1978 International Conference on Communications, vol. 1, 1978, pp. 8.3.1-8.3.5. |
Continuations (2)
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Number |
Date |
Country |
Parent |
668188 |
Nov 1984 |
|
Parent |
361091 |
Mar 1982 |
|