Claims
- 1. A method for fabricating a chip, comprising the steps of:
forming a first oxide layer over a substrate; forming a first die boundary channel in said first oxide layer that extends down through said first oxide layer and to said substrate; forming a dielectric layer over said first oxide layer and within at least a lower portion of said first die boundary channel; defining first and second die on opposite sides of at least a portion of said first die boundary channel, wherein each said die comprises a microelectromechanical assembly; and separating said first die from said second die at least along a portion of said first die boundary channel.
- 2. A method, as claimed in claim 1, wherein said forming a first die boundary channel step comprises patterning said first oxide layer.
- 3. A method, as claimed in claim 1, wherein said forming a first die boundary channel step comprises defining first and second sidewalls of said first die boundary channel with first and second edge surfaces, respectively, of said first oxide layer.
- 4. A method, as claimed in claim 3, wherein said first and second edge surfaces of said first oxide layer are separated by a distance within a range of about 50 microns to about 300 microns.
- 5. A method, as claimed in claim 3, wherein said first and second edge surfaces of said first oxide layer are disposed in at least generally parallel relation.
- 6. A method, as claimed in claim 3, wherein said forming a dielectric layer step comprises coating said first and second edge surfaces of said first oxide layer with a dielectric material.
- 7. A method, as claimed in claim 1, wherein said forming a first die boundary channel step comprises defining a closed perimeter for said first die boundary channel, wherein said first die is surrounded by said first die boundary channel.
- 8. A method, as claimed in claim 1, wherein said forming a dielectric layer step comprises filling only a lower portion of said first die boundary channel with a dielectric material.
- 9. A method, as claimed in claim 1, wherein said forming a dielectric layer step comprises protecting said first oxide layer from exposure to a release etchant to which said chip is exposed after said separating step.
- 10. A method, as claimed in claim 1, wherein said defining first and second die step comprises using a field stepper.
- 11. A method, as claimed in claim 1, wherein:
said defining first and second die step comprises forming an identical said microelectromechanical assembly on each of said first and second die.
- 12. A method, as claimed in claim 11, wherein said defining first and second die step comprises forming all microstructures of said microelectromechanical assembly for each of said first and second die outside of said first die boundary channel.
- 13. A method, as claimed in claim 1, wherein said separating step comprises sawing at least generally along said at least a portion of said first die boundary channel.
- 14. A method, as claimed in claim 1, wherein said defining first and second die step comprises forming at least one electrical trace that extends across said at least a portion of said first die boundary channel directly on said dielectric layer.
- 15. A method, as claimed in claim 14, further comprising the step of forming a shield over only a portion of each said electrical trace such that said separating step fails to pass through any portion of any said shield.
- 16. A method, as claimed in claim 15, wherein said separating step defines a first edge of said chip, wherein each said shield is separated from said first edge by a distance of at least about 25 microns.
- 17. A method, as claimed in claim 1, wherein said defining first and second die step comprises forming a first electrical trace for said first die that is located out of said first die boundary channel, forming a second electrical trace for said second die that is located out of said first die boundary channel, forming a third electrical trace on said dielectric layer within said first die boundary channel, forming a first jump connection between said first and third electrical traces, and forming a second jump connection between said second and third electrical traces.
- 18. A method, as claimed in claim 17, wherein a first portion of said third electrical trace is associated with said first die and a second portion of said third electrical trace is associated with said second die, and wherein ends of said first and second portions of said third electrical trace are merged together.
- 19. A method, as claimed in claim 17, wherein said forming a dielectric layer step comprises forming a second die boundary channel within said first die boundary channel, wherein said second die boundary channel comprises a base and first and second sidewalls that are defined by a dielectric material, wherein said third electrical trace terminates prior to reaching said first sidewall of said second die boundary channel and prior to reaching said second sidewall of said second die boundary channel.
- 20. A method for fabricating a chip, comprising the steps of:
forming a plurality of rows and columns of die on a wafer, wherein each of said die is identical and comprises a first microelectromechanical assembly; and electrically interconnecting at least one of each adjacent pair of said die in each of said columns and each said adjacent pair of said die in each of said rows such that a first chip of a first number of said die may be formed from said wafer and that a second chip of a second number of said die may be formed from said wafer, wherein said first number is different from said second number.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This patent application is a divisional of, and claims priority under 35 U.S.C. §120 to, U.S. patent application Ser. No. 10/099,139, that was filed on Mar. 16, 2002, and that is entitled “MULTI-DIE CHIP AND METHOD FOR MAKING THE SAME”, the entire disclosure of which is incorporated by reference in its entirety herein.
Divisions (1)
|
Number |
Date |
Country |
Parent |
10099139 |
Mar 2002 |
US |
Child |
10456319 |
Jun 2003 |
US |