Patent Application
20110165758
The invention relates to a method for making a structure intended for applications in the fields of electronics, optics or optoelectronics, which comprises a thin layer of semiconducting material on a substrate.
Preferentially, this method is of the type including the steps of:
But this method may also be of the kind in which:
Methods of the aforementioned type are already known; these are for example methods of the Smart Cut (registered trade mark) type. More extensive details will be found relating to the Smart Cut process in the document Silicon-On-Insulator Technology: Materials to VLSI, 2nd Edition of Jean-Pierre Colinge at Kluwer Academic Publishers, p. 50 and 51.
With such methods, it is possible to advantageously make structures comprising a thin layer of semiconducting material on a supporting substrate and notably SOI (Semiconductor On Insulator) type structures, in which an insulating layer is inserted inbetween the thin layer and the supporting substrate.
The structures obtained by such methods are used for applications in the fields of microelectronics, optics and/or optoelectronics, the thin layer being typically used as an active layer for forming components.
Stabilization of the adhesive bonding interface between the thin layer and the supporting substrate proves to be necessary so that the obtained structure after detachment has mechanical and electrical properties which comply with the requirements and specifications of the fields of application of the invention.
The question is to notably ensure strong adhesion of the thin layer and of the supporting substrate. In the absence of such adhesion, there is a risk that the subsequent steps for forming electronic components lead to delamination of the thin layer at the adhesive bonding interface.
On this subject, it is noted that in the absence of a treatment at least aiming at reinforcing the adhesive bonding interface, immersion in a bath such as an HF bath for example, directly after detachment, of the structure formed according to a Smart Cut type method, leads to detachment of the thin layer at the periphery of the structure, over a radial extension of several microns, or even to total detachment of the thin layer.
Moreover, the quality of the adhesive bond at the adhesive bond interface is capable of changing the behavior of the carriers in the thin layer. In order to ensure satisfactory and reproducible electric performances, it is therefore required that the adhesive bonding interface be stabilized.
Partial solutions to the problem of stabilization of the adhesive bonding interface have been proposed. The latter recommend that a strong adhesive bond be made between the donor substrate and the supporting substrate, typically by providing thermal energy between the adhesive bonding and detachment steps, or even by carrying out before the adhesive bonding step a treatment for preparing either one and/or both of the surfaces to be adhesively bonded. But with these “pre-stabilization” treatments, it is not generally possible to obtain an interface with sufficient quality in terms of mechanical strength and/or electric performance.
In order to achieve real stabilization of the adhesive bonding interface between the thin layer and the supporting substrate, a heat treatment of the obtained structure after detachment and transfer of the thin layer from the donor substrate to the supporting substrate is typically carried out today.
More specifically, this treatment is annealing in an oven of the structure obtained after detachment, at a temperature of the order of 1,000 to 1,200° C., for one to two hours, depending on the nature of the materials of the structure (nature of the upper layer, of the supporting substrate and of the insulator). This is termed as stabilization annealing.
The defects possibly present at the adhesive bonding interface are visible on sample photographs of the section of a structure, taken with an electronic transmission microscope, possibly after a treatment aiming at making these defects better visible, as this is detailed in FR2903809.
Indeed, light areas are identified therein, which correspond to “open” spaces, i.e. distances between atoms which are larger than normal distances.
In any case, applying a temperature of the order of 1,000° C. to 1,200° C. in order to perfect the adhesive bonding interface has a certain number of constraints.
Thus, notably industrially, its application requires resorting to unconventional ovens.
Further, depending on the structure on which the adhesive bonding is carried out, the application of such a high temperature may damage it. This is the case when the materials of the upper layer and of the supporting substrate have different thermal expansion coefficients. This is also the case when one of the materials cannot be exposed to a too high temperature, such as for example germanium, for which the melting temperature is of the order of 900° C.
The present invention therefore aims at solving this problem by proposing a method of the kind mentioned above, with which a perfect adhesive bonding interface may be obtained, without having to resort to so high temperatures of stabilization annealing.
Thus, it relates to a method for making a structure notably intended for applications in the fields of electronics, optics or optoelectronics, which comprises a thin layer of semiconducting material on a supporting substrate, according to which:
characterized by the fact that prior to step b), atoms from the thin layer are transferred to the supporting substrate and/or from the supporting substrate to the thin layer, by implanting ions at said interface.
With this treatment by implanting ions, it is somewhat proceeded with “damaging” of the region of the interface and with a rearrangement of the atoms.
This is expressed by better adhesive bonding of the interface, which requires lower stabilization annealing temperatures.
According to other advantageous and non-limiting features of this method:
Other features and advantages of the present invention will become apparent upon reading the description which follows of a preferential embodiment. This description will be given with reference to the appended drawing wherein
A thin layer, for example in silicon, provided with an oxide thickness is referenced therein as 1, and a supporting substrate, for example also in silicon with an oxide thickness, as 3. The oxidized surfaces of the layer 1 and of the supporting substrate 3 are put into contact and are adhesively bonded to each other by molecular adhesion, at an identified interface 2.
As stated above, the present invention may be considered as a mixing of the interface 2, by means of ion implantation, in order to damage the oxide/oxide interface in the case of this embodiment, and to rearrange the atoms in this region, so as ensure perfect cohesion between the layers 1 and 3 of the structure.
The parameters of this implantation are most particularly:
Preferably, the implanted ions are of the same nature as those present at the interface.
After the implantation, stabilization annealing is performed which allows oxygen to be diffused and the crystalline defects to be cured. A temperature of 800 or 900° C. may be sufficient for this purpose.
It is also possible to consider carrying out the implantation, not at room temperature but at a temperature of about 300° C., by which damaging may be limited and the duration of the stabilization annealing may be reduced.
This is particularly advantageous for the structures in which one of the materials may become damaged if it is subject to too high a temperature.
Finally, a relatively uniform oxide layer is obtained in which the interface is no longer distinct, because the structure has been perfectly reformed.
During implantation, it is sought not to damage too much the material (silicon) on either side of the oxide. Indeed, implantation will have the effect of amorphizing silicon, which will recrystallize upon stabilization annealing, but by letting defects remain, of the so-called “end of range”, i.e. end of travel, type.
It is specified that with view to the implantation, the thickness of the “top” thin layer should be sufficiently thin so that it may be crossed by the ions. If a thick “top” layer is desired, a solution is to carry out epitaxy after implantation. In this case the damaging of the material is moreover less critical.
In the case of an intermediate Si02 layer and of co-implantation of Si ions and oxygen ions, the ions will preferably be implanted in the same stoichiometric ratio as SiO2 present at the interface. The implantation energy will be determined so that the ions are mainly distributed in the region of the interface.
The implantation may also be applied just after forming the thin layer. However, when the latter is thinned by successive oxidation of its free surface and removal of the thereby formed oxide in order to form an ultra-thin layer, the implantation may then be carried out after the last oxidization cycle/removal of the oxide.
An 501 structure (of the Si/SiO2/Si type) obtained according to the Smart Cut™ method, is used, for which the adhesive bonding interface was formed by putting into contact the silicon oxide present on the side of the top thin layer and on the side of the support.
The total thickness of the oxide layer is 10 nm, whereas that of the top thin layer is from 300 to 400 nm. The implantation of Si ions takes place just after the detachment which occurs during the Smart Cut™ method of the thin layer.
It is proceeded with implantation of Si ions at an energy of 300 keV, at room temperature, and at a dose of 1015at/cm2, which leads to onset of amorphization around the depth of the order of 340 mm. This should be sufficient according to the literature, for producing effective “mixing”.
This non-amorphizing implantation is followed by standard finishing steps, notably by annealing at a temperature below 1,200° C., for example comprised between 800° C. and 900° C.
An increase in the dosage of ions in order to obtain 3×1015at/cm2 leads to the creation of an amorphous buried silicon layer, centered around the fine buried oxide layer. During the subsequent heat treatments and the steps for thinning the upper layer, this amorphous layer may recrystallize by epitaxy in the solid phase (briefly SPE, for “Solid Phase Epitaxy”). The “end of range” defects in the upper layer may be removed during the thinning of the thin layer. Those positioned below (i.e. in the supporting substrate), which will remain, themselves form a layer for trapping defects.
Structure of Si/SiO2/sapphire type.
This structure is made in the following way; an SOI substrate having a 300 to 400 nm upper layer, a 100 nm buried oxide and an Si supporting substrate of the order of 700 microns, is oxidized in order to form a 100 nm surface oxide.
The oxidized upper layer of this substrate is put into contact with a sapphire substrate and the assembly is annealed at a low temperature (because of the thermal expansion coefficient difference which does not allow exposure of this assembly to too high a temperature), of the order of 300° C. to 600° C.
The silicon support as well as the buried oxide of the initial SOI substrate is removed by the successive grinding and etching steps.
Finally, the aforementioned Si/SiO2/sapphire structure is then obtained. The adhesive bonding interface in this case is located between the oxide layer and the sapphire support.
The thickness of the oxide layer is 10 nm and that of the top thin layer is from 300 to 400 nm. The sapphire support has a thickness of several hundred microns.
Silicon and oxygen ions are implanted sequentially.
Si ions are implanted under an energy of about 300 keV.
O ions are implanted under an energy of about 180 keV.
The total implantation dose should be kept below the amorphization threshold, which is estimated to be 2.1015at/cm2.
Respective doses of Si/O ions of the order of ½ are used in order to avoid distortions of the stoichiometry of the oxide layer.
The “standard” finishing steps are applied for completing the method, for example for thinning the top thin layer to its desired final thickness.
Structure of the Si/SiO2/Si type, similar to that of Example 1.
The thickness of the oxide layer is 10 nm and that of the thin layer from 300 to 400 nm.
The implantation takes place after detachment of the thin layer.
The Si ions are first implanted under an energy of 300 keV, at a dose of 2×1016at/cm2. The implantation temperature is slightly below 200° C. It is estimated that this implantation creates amorphization of Si in the thin layer at a depth of about 100-150 nm.
Oxygen implantation is then carried out with an energy of about 180 keV, at 400° C. and at a dose of 4×1016at/cm2, and this leads to complete IBIEC of the layer of amorphized Si, in order to reform a layer with satisfactory crystalline quality.
The standard finishing steps may be applied for perfecting the method.
It will be noted that the present invention is not limited to a method in which adhesive bonds apply one or two adhesive bonding layers in silicon oxide. In particular, it is applicable regardless of the nature of the materials present at the adhesive bonding interface.
For example these may be amorphous materials such as Si3N4 or crystalline materials.
This is notably the case when the thin layer exclusively consisting of a crystalline material is put into direct contact with the support, itself crystalline or polycrystalline.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0855447 | Aug 2008 | FR | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP09/58434 | 7/3/2009 | WO | 00 | 12/13/2010 |
