Patent Application
20250107251
This application claims priority to Chinese patent application No. 202311234811.3, filed on Sep. 22, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present application relates to semiconductor making technology and, in particular, to a method for making an image sensor.
For small-pixel image sensors produced by a conventional Fab (fabrication, a chip maker) as shown in
A method in the prior art for forming a CMOS image sensor includes: providing a device wafer, dividing it into a logical area, and a pixel area, spacing the logical area from the pixel area by a shallow trench isolation structure, wherein the pixel area includes a photoelectric conversion area and a pixel transistor area, and the photoelectric conversion area is adjacent to the pixel transistor area. Then, a gate is formed on the logical area and the pixel area, respectively, and the gate of the pixel area is located on the pixel transistor area. Next, a first side wall is formed at both sides of the gates of the logical area and the pixel area, the first side wall of the pixel area is located in the pixel transistor area, a dielectric layer exactly covering the first side wall is formed on the first side wall, and a second side wall exactly covering the dielectric layer is formed on the dielectric layer. However, the second side wall is formed by the following process: first forming a silicon nitride layer covering upper surfaces of a dielectric layer and a first gate, and a surface of a device wafer between the first gate and second gate, and then a portion of the silicon nitride layer is etched to form a second side wall which exactly covers the dielectric layer, and does not cover a surface of a device wafer of a photoelectric conversion area.
Damage is caused to a surface of a device wafer in a PD area because a device wafer is wholly etched during etching of a silicon nitride layer when making a CMOS image sensor in an existing method for forming the sensor. Large-pixel CMOS (a pixel size>5 um) image sensors may be subjected to more serious surface etching damage because an etching area is relatively large during poly etch due to a relatively shallow N-type injection for PD areas. Additionally, the large-pixel sensors may have poor pixel area performance because a relatively serious plasma interference is caused for the device wafer surface of the PD area during poly etch and further a dark current is produced in which the dark current is produced within the sensors by non-light factors without lighting. Further, the dark current may have lethal effects on the imaging quality of the security products derived from the large-pixel sensors due to a relatively small photocurrent under a low illumination environment.
Additionally, an oxide layer formed in the PD area is very shallow before polysilicon generation in the prior art CMOS process, and a DG (Dual gate, dual gate) process can only enable a surface oxide layer of about 70 Å. Thus, blocking is insufficient during poly etch.
The present disclosure provides a method for making an image sensor, wherein blanket etch can be performed for the surface of the PD areas during subsequent DG-ET (double-gate etch) and poly etch, and damage to the surface caused by etching can be avoided, reducing the plasma interference, and ultimately, the pixel dark current to improve pixel performance.
The method for making an image sensor, including the following steps:
In some examples, in step S3, the supplementary oxide layer 114 is a high-temperature oxide film grown on the wafer surface by using a furnace tube process.
In some examples, the high temperature oxide film is obtained by reacting SiH4 with H20 at 750° C.-850° C.
In some examples, the supplemental oxide layer 114 has a thickness of 140 Å-160 Å.
In some examples, the first gate oxide layer 116 has a thickness of 40 Å-60 Å.
In some examples, the subsequent processes comprise:
In some examples, the polysilicon hard mask layer 120 is SIN-SIO2-SIN from bottom to top.
In some examples, the image sensor has a pixel unit size greater than 5 um.
In the method for making an image sensor of the present application, the additional supplementary oxide layer 114 is added in a PD area of a pixel cell before the formation of a gate oxide layer, a layer of a first photoresist (a COX1 photoresist) is added, photoetching is used to define a PD area of a non-pixel cell, and the supplementary oxide layer 114 on the wafer surface outside the PD area is removed by etching, retaining the supplementary oxide layer 114 in the PD area. Thus, a relatively thick oxide layer can be formed in the PD area before polysilicon generation, blanket etching can be performed on the surface of the PD area during subsequent DG-ET (double-gate etching) and poly etch, and surface damage can be avoided during etching, reducing the plasma interference, and ultimately, the pixel dark current to improve pixel performance. The image sensor making method, as the optimization to the existing mature process, can be performed by using existing equipment, and is easy to implement and can significantly improve the dark current with few side effects.
The figures required for the present application are briefly introduced hereafter to illustrate the technical solution of the application more clearly. It is obvious that the figures described below are only some embodiments of the application, and that other figures can be obtained by those skilled in the art based on these figures without creative labor.
The technical solutions in the embodiments of the present application may be described clearly below in conjunction with the figures in the embodiments. It is obvious that the described embodiments are only some of the embodiments of the application. The scope of protection of the present application encompasses all other embodiments obtained by those skilled in the art without creative labor based on the embodiments of the application.
Terms such as “first”, “second”, etc. in the present application do not indicate any order, number, or importance, but are only to distinguish different parts. The phasing “including”, “comprising”, etc. means that the element or object preceded by the phasing covers the element or object and equivalents thereof listed below the phasing, but does not exclude other elements or objects. The expression such as “connected”, “coupled”, etc. is not limited to physical or mechanical connections, but may include direct or indirect electrical connections. “Upper”, “lower”, “left”, “right”, etc. are used only to indicate relative positional relations. When an absolute position of a described object is changed, the relative positional relations may also be changed accordingly.
It should be noted that the embodiments of the present application and the features thereof may be combined with each other without contradictory.
As shown in
In the method for making an image sensor in embodiment I, the additional supplementary oxide layer 114 is added in a PD area of a pixel cell before the formation of a gate oxide layer, a layer of a first photoresist (a COX1 photoresist) is added, photoetching is used to define a PD area of a non-pixel cell, and the supplementary oxide layer 114 on the wafer surface outside the PD area is removed by etching, retaining the supplementary oxide layer 114 in the PD area. Thus, a relatively thick oxide layer can be formed in the PD area before polysilicon generation, blanket etching can be performed on the surface of the PD area during subsequent DG-ET (double-gate etching) and poly etch, and surface damage can be avoided during etching, reducing the plasma interference, and ultimately, the pixel dark current (it is expected that the dark current can be reduced by 25%) to improving pixel performance. The image sensor making method, as the optimization to the existing mature process, can be performed by using existing equipment, and is easy to implement and can significantly improve the dark current with few side effects.
This embodiment is based on the image sensor making method of example I, and in step S3, the supplemental oxide layer 114 is a high-temperature oxide (HTO) film grown on the wafer surface by using a furnace tube process.
In some examples, the high temperature oxide (HTO) film is silicon dioxide (SiO2) or silicon tetrachloride (SiO4) obtained by reacting silane (SiH4) with H2O at 750° C.-850° C. (e.g., 850° C.).
In some examples, the supplemental oxide layer 114 has a thickness of 140 Å-160 Å (e.g., 150 Å).
In some examples, the first gate oxide layer 116 has a thickness of 40 Å-60 Å (e.g., 50 Å)
In the image sensor making method of embodiment II, the high temperature oxide (HTO) film in the PD area is retained, and subsequently, a gate oxide layer of about 50 Å is further grown at the interface between the high temperature oxide (HTO) film and silicon, so as to increase the overall thickness of the oxide layer on the PD area to about 200 Å, and thus, effective blocking for the PD area is generated during subsequent poly etch.
This embodiment is based on the method for making an image sensor of example I, and includes subsequent processes comprising:
In some examples, the polysilicon hard mask layer 120 is SIN-SIO2-SIN from bottom to top.
In some examples, the image sensor is a CMOS image sensor with a pixel cell size (a pixel size) greater than 5 um.
The embodiments described above are only preferred embodiments of the present application and are not intended to limit the present application. The scope of protection of the application shall include any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311234811.3 | Sep 2023 | CN | national |
