Claims
- 1. A method for manufacturing a semiconductor apparatus which has second conductivity type emitter region and collector region and a first conductivity type base region arranged in a lateral direction within a first conductivity type element forming region which is surrounded from its side portions and its lower portion by an insulating layer, comprising the steps of:
- providing the element forming region;
- forming an interlayer on said element forming region;
- forming an opening portion on said interlayer at a portion corresponding to a portion which will become said emitter region;
- selectively forming a semiconductor layer on said opening portion so that a part of said semiconductor layer is overgrown over said interlayer in the lateral direction; and
- introducing a second conductivity type impurity into one side of said element forming region and said semiconductor layer while preventing introduction in the other side of said element forming region;
- introducing a first conductivity type impurity in said other side of the element forming region; and
- heat treating to diffuse the second conductivity type impurities to form the collector and emitter.
- 2. A method according to claim 1, which includes providing the element forming region by providing a first substrate of the first conductive type having a step to form an element forming region, forming an SiO.sub.2 layer surrounding said element forming region, bonding another substrate with an SiO.sub.2 layer onto the element forming region and then polishing away the first substrate to expose the element forming region.
- 3. A method according to claim 1 wherein the step of providing the element forming region provides the region in two sub-regions interconnected by an underlying conductive layer.
- 4. A method for manufacturing a semiconductor apparatus which has a first conductivity type emitter region and collector region and a second conductivity type base region arranged in the lateral direction within a first conductivity type element forming region which is surrounded on its side portions and its lower portion by an insulating layer, comprising the steps of:
- providing the element forming region;
- forming an island-shaped insulating layer on said element forming region;
- selectively introducing an impurity for forming a second conductivity type base region into one side of said element forming region under the state that said island-shaped insulating layer is employed as a mask; and
- forming a semiconductor layer serving as an emitter diffusion layer on a part of said element forming region in which said impurity is introduced so that said semiconductor layer includes a pair of an upper surface of said island-shaped insulating layer.
- 5. A method according to claim 4, which includes providing the element forming region by providing a first substrate of a first conductive type having steps to form an element forming region, forming an SiO.sub.2 layer surrounding said element forming region, bonding another substrate with an SiO.sub.2 layer onto the element forming region and then polishing away the first substrate to expose the element forming region.
- 6. A method according to claim 4, wherein a conductive layer for a base electrode is formed in advance on an under layer of one side of said element forming region.
- 7. A method for manufacturing a semiconductor apparatus which has a first conductivity type emitter region and collector region and a second conductivity type base region arranged in a lateral direction within a first conductivity type element forming region which is surrounded on its side portions and its lower portion by an insulating layer, comprising the steps of:
- providing the element forming region;
- forming an island-shaped insulating layer on said element forming region;
- forming a semiconductor layer on a part of one side of said element forming region so that said semiconductor layer includes a part of an upper surface of said island-shaped insulating layer;
- introducing an impurity for forming a second conductivity type base region into said exposed semiconductor layer under the state that the other side of said element forming region is masked; and
- introducing an impurity for forming a first conductivity type emitter region into said exposed semiconductor layer under the state that the other side of said element forming region is masked.
- 8. The method for manufacturing a semiconductor apparatus according to claim 7, wherein a conductive layer for a base electrode is formed in advance on an under layer of one side of said element forming region.
- 9. A method according to claim 7, which includes providing the element forming region by providing a first substrate of the first conductive type having a step to form an element forming region, forming an SiO.sub.2 layer surrounding said element forming region, bonding a second substrate with an SiO.sub.2 layer onto the element forming region and subsequently polishing away the first substrate to expose the element forming region.
Priority Claims (2)
Number |
Date |
Country |
Kind |
3-330561 |
Dec 1991 |
JPX |
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3-330562 |
Dec 1991 |
JPX |
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Parent Case Info
This is a division of application Ser. No. 07/989,514, filed Dec. 11, 1992, now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0241167 |
Sep 1989 |
JPX |
0246871 |
Oct 1989 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Higaki et al., "A Thin-Base Lateral Bipolar Transistor Fabricated on Bonded SOI", Autumn Meeting Held by Institute of Society of Electronics, Information and Communication Engineers, 1991, pp. SC-9-8, 5-216, 5-217. |
Divisions (1)
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Number |
Date |
Country |
Parent |
989514 |
Dec 1992 |
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