Patent Application
20230025429
The present invention relates to a method for manufacturing a semiconductor-on-insulator structure, in particular for radiofrequency applications. The invention also relates to a semiconductor-on-insulator structure obtained by implementing this method.
Semiconductor-on-insulator structures are multilayer structures comprising a substrate that is generally made of silicon, an electrically insulating layer arranged on the substrate, which is generally an oxide layer such as a silicon oxide layer, and a semiconductor layer arranged on the insulating layer, which is generally a silicon layer.
Such structures are referred to as “Semiconductor-On-Insulator” structures (SeOI), in particular “Silicon-On-Insulator” (SOI) when the semiconductor material is silicon.
Among the existing SOI structures, the structures referred to as “Fully-Depleted Silicon-On-Insulator” (FD-SOI) structures are commonly used for digital applications. FD-SOI structures are characterized by the presence of a thin oxide layer, arranged on a silicon support substrate, and a very thin semiconductor layer arranged on the oxide layer, called SOI layer.
The oxide layer is located between the substrate and the SOI layer. The oxide layer is then referred to as “buried”, and is called “BOX” for “Buried OXide”.
The SOI layer allows the conduction channel of the FD-SOI structure to be implemented.
Due to the low thickness and the uniformity of the BOX layer and of the SOI layer, the conduction channel does not need to be doped, hence the structure can operate in a fully depleted mode.
FD-SOI structures have improved electrostatic features compared to structures without a BOX layer. The BOX layer decreases the parasitic electrical capacitance between the source and the drain, and also allows any electron leakage from the conduction channel to the substrate to be considerably reduced by confining the flow of electrons in the conduction channel, thereby reducing any electrical current losses and improving the performance capabilities of the structure.
FD-SOI structures can be compatible with radiofrequency (RF) applications, yet nevertheless suffer from the occurrence of electrical losses in said substrate.
In order to compensate for these electrical losses and to improve the RF performance capabilities, the use of a substrate is known, in particular of the SOI type, with high electrical resistivity, with this type of substrate commonly being called an “HR substrate” (High-Resistivity substrate). This HR substrate is advantageously combined with a charge-trapping layer (or “trap-rich layer”).
However, this type of substrate is not compatible with the use of transistors with a threshold voltage that must be controlled via a back-side gate (back-bias voltage). Indeed, the presence of this layer comprising trapped charges hinders back biasing (application of a potential difference to the back face).
The scientific publication entitled “Low loss Si-substrates enhanced using buried PN junctions for RF Applications” (M. Rack, L. Nyssens, and J-P. Raskin, IEEE Electron device letters, vol. 40, Issue 5) describes the formation of P-N junctions laterally arranged under the electrically insulating layer of a substrate intended for radiofrequency applications.
Laterally is understood to mean that two respectively P-doped and N-doped regions are arranged at the same depth of the substrate, with the junction between said regions being substantially perpendicular to the main surface of the substrate. Such a junction is obtained by implanting phosphorus over the whole substrate for N-type doping, followed by localized implantation of boron through a mask in order to form P-doped regions, then thermal treatment for activating the dopants.
Whilst a doped semiconductor is a good conductor, the junction hardly lets through any electrical current, thereby preventing the propagation of parasitic electric fields.
One disadvantage resulting from a lateral arrangement of the P-N junction as described in the scientific publication is that it requires a lithography step for forming the mask and two implantation steps, which represents a significant additional expense.
An aim of the invention is to propose a method for manufacturing a semiconductor-on-insulator structure that allows the aforementioned disadvantages to be overcome.
The aim of the invention is to propose such a manufacturing method for manufacturing an FD-SOI structure exhibiting good radiofrequency performance capabilities.
To this end, the invention proposes a method for manufacturing a semiconductor-on-insulator structure, comprising the following steps:
in order to form, in the substrate, a first N-type doped region extending between the base of the substrate and the P-N junction and a second P-doped region located between the first region and the electrically insulating layer.
The main technique for measuring interstitial oxygen in the silicon of a semiconductor substrate is infrared absorption using Fourier Transform InfraRed (FTIR) spectrometry.
This FTIR measurement provides a value of an absorption coefficient αOX due to the interstitial oxygen. The interstitial oxygen concentration is computed on the basis of this absorption coefficient αOX, in accordance with the method that is particularly described in the document entitled “A Study of Oxygen Precipitation in Heavily Doped Silicon” (1989), Graupner, Robert Kurt, Dissertations and Theses, Paper 1218.
According to this method, the oxygen concentration as atoms per cm3 (at/cm3) or as a fraction of the total number of atoms present in parts per million (ppma) is obtained by multiplying the absorption coefficient αOX by a conversion factor.
The oxygen concentration referred to in the invention (old ppma) is obtained by using the first of the four conversion factors presented in the following list, called “old ASTM” (American Society for Testing), expressed as ppma:
According to other aspects, the manufacturing method of the invention has the different following features taken alone or according to their technically possible combinations:
The invention also relates to a semiconductor-on-insulator structure obtained directly by implementing the previously described manufacturing method, wherein said semiconductor-on-insulator structure successively comprises, from its base to its top:
According to other aspects, the structure of the invention has the different following features taken alone or according to their technically possible combinations:
Further advantages and features of the invention will become apparent upon reading the following description, which is provided by way of an illustrative and non-limiting example, with reference to the following appended figures, in which:
The invention relates to a method for manufacturing a semiconductor-on-insulator structure, as well as such a structure.
The manufacturing method of the invention allows semiconductor-on-insulator structures to be manufactured that comprise a P-N junction imparting good radiofrequency properties to said structure, and so doing in a simple and inexpensive manner.
An FD-SOI substrate, schematically shown in
The monocrystalline substrate 2 is a substrate with high electrical resistivity, and thus has electrical resistivity ranging between 500 Ω·cm and 30 kΩ·cm.
In addition, the monocrystalline substrate 2 is a substrate with a high amount of oxygen, and thus has an interstitial oxygen content (Oi) ranging between 20 and 40 old ppma. The oxygen is trapped in the structure of the monocrystalline substrate, more specifically in the interstices located between the grains of the material forming the monocrystalline substrate, and is therefore called “interstitial oxygen”.
The monocrystalline substrate with high electrical resistivity and a high amount of interstitial oxygen is also referred to as an HR HiOi (which is a combination of the acronyms for “High Resistivity” and “High Oxygen”) substrate.
Preferably, the monocrystalline substrate is made of silicon.
The monocrystalline substrate has P- or N-type doping.
In the case of N-type doping, the monocrystalline substrate 2 is preferably doped with phosphorus, and, more preferably, the monocrystalline substrate is made of phosphorus-doped silicon.
In the case of P-type doping, the monocrystalline substrate 2 is preferably doped with boron, and, more preferably, the monocrystalline substrate is made of boron-doped silicon.
The thickness of the electrically insulating layer 3, also referred to as a BOX layer in that it is arranged between the underlying monocrystalline substrate 2 and the overlying monocrystalline layer 4, ranges between 20 nm and 400 nm.
Preferably, the electrically insulating layer 3 comprises a silicon oxide layer.
The monocrystalline layer 3 has P-type doping.
Preferably, the monocrystalline layer is a silicon layer.
According to the method of the invention, a heat treatment is applied to the FD-SOI substrate at a temperature greater than or equal to 1175° C., for a time greater than or equal to 1 hour.
During said heat treatment, a P-N junction, reference sign 5, is formed in the monocrystalline substrate 2 at a determined depth with respect to the electrically insulating layer 3, as illustrated in
More specifically, the heat treatment causes the following phenomena.
On the one hand, P-type dopants of the monocrystalline layer diffuse into the monocrystalline substrate through the electrically insulating layer, in a region of the substrate neighboring the electrically insulating layer.
On the other hand, when the monocrystalline substrate is P-doped, the type of doping in the monocrystalline substrate 2 is inverted.
Combining these two phenomena produces a region 6, called first region, in the substrate, which region extends from the base of the monocrystalline substrate to the P-N junction and which is N-type doped due to the inversion of the type of doping. The P-N junction then marks the boundary between the first region 6, and the remaining region 7, called the second region, of the monocrystalline substrate, which region extends from the P-N junction to the electrically insulating layer 3 and which remains P-doped, with the diffusion of the P-type dopants in this second region having compensated for the inversion of the type of doping.
When the monocrystalline substrate is N-doped, the aforementioned phenomenon of diffusing P-type dopants in the second region occurs. However, the phenomenon of inverting the type of doping does not occur. Consequently, the first region remains N-type doped.
Irrespective of the initial type of doping of the monocrystalline substrate, on completion of the heat treatment, the monocrystalline substrate comprises a P-N junction separating the first N-type doped region (located next to the base of the substrate) and the second P-type doped region (located next to the electrically insulating layer).
The P-N junction can be formed due to the following three features:
The presence of the P-N junction associated with the high electrical resistivity of the crystalline substrate 2, ranging between 500 Ω·cm and 30 kΩ·cm, allows a structure to be obtained that exhibits very good radiofrequency properties. These properties will be illustrated throughout the remainder of the present document. Adjusting these three features allows the formation of the P-N junction to be controlled, and in particular its depth in the monocrystalline substrate 2 from the electrically insulating layer 3.
The parameters of the method, such as, for example, the three aforementioned features, are adjusted so as to form the P-N junction at a depth ranging between 1 μm and 5 μm from the electrically insulating layer.
In the case of a P-type monocrystalline substrate, the heat treatment causes the interstitial oxygen present in the monocrystalline substrate 2 to precipitate, which forms sulfur oxide SxOy heat donors provided with surplus charges for doping the material of the monocrystalline substrate, and thereby reversing the doping thereof. This first phenomenon is schematically shown in
Furthermore, whether or not the monocrystalline substrate is N- or P-type doped, the heat treatment causes the dopants of the monocrystalline layer 4, such as boron, to diffuse through the electrically insulating layer 3, which is thin enough, into the monocrystalline substrate 2. These dopants also can be used to control the formation of the P-N junction, and in particular its depth in the monocrystalline substrate from the electrically insulating layer. This second phenomenon is schematically shown in
This second phenomenon, combined with the first in the case of a P-type doped monocrystalline substrate, lead to the formation of the first region of the N-doping substrate, and to the formation of the second P-doped region, located between the first region and the electrically insulating layer, shown on the semiconductor-on-insulator structure 10 of
The method of the invention offers the advantage of allowing these two phenomena to occur by virtue of the three previously listed features, without needing additional processing steps. In particular, unlike the lateral P-N junction described in the aforementioned article by M. Rack et al., forming the P-N junction in the thickness of the substrate in the present invention does not require any localized implantation of dopants or any mask to be deposited on the substrate.
According to a preferred embodiment, the FD-SOI substrate is obtained by transferring a layer of a donor substrate onto a recipient substrate.
According to a first alternative of this embodiment illustrated in
The monocrystalline layer 24 to be transferred preferably is a silicon layer.
A monocrystalline recipient substrate 30, preferably made of silicon, is also provided with electrical resistivity ranging between 500 Ω·cm and 30 kΩ·cm, an interstitial oxygen content (Oi) ranging between 20 and 40 old ppma, and P- or N-type doping.
With reference to
The electrically insulating layer 22 can originate from the donor substrate or from the recipient substrate, i.e., it initially can be located on the donor substrate or on the receiver substrate prior to bonding.
With reference to
Preferably, the layer 24 is transferred from the donor substrate 20 to the recipient substrate 30 in accordance with the Smart Cut™ method, in which the embrittlement zone 23 is formed by implanting atomic species such as, for example, hydrogen and/or helium atoms, in the donor substrate, then the donor substrate is detached along said embrittlement zone.
According to a second alternative of this embodiment illustrated in
The monocrystalline layer 21 preferably is a silicon layer.
A monocrystalline recipient substrate 30, preferably made of silicon, is also provided with electrical resistivity ranging between 500 Ω·cm and 30 Ω·cm, an interstitial oxygen content (O) ranging between 20 and 40 old ppma, and P- or N-type doping.
With reference to
The electrically insulating layer 22 can originate from the donor substrate or from the recipient substrate, i.e., it initially can be located on the donor substrate or on the receiver substrate prior to bonding.
With reference to
The good radiofrequency properties of the semiconductor-on-insulator structure obtained by the previously described method are illustrated with reference to
The gain HD2 corresponds to the second harmonic, measured at a frequency of 900 Mhz.
More specifically, HD2 is the harmonic generated by the substrate capable of interfering with the operation of a radiofrequency device comprising the structure according to the invention. The weaker the HD2, the more insulating the substrate. The HD2 is measured across a coplanar line with an input point and an output point. At the input point, a power Pin(dBm) is imposed, and at the output the power Pout is measured, which is broken down into several harmonics, in particular including HD1, which corresponds to the power measured at the output that is approximately equal to the input power, and HD2, which corresponds to the harmonic generated by the substrate.
According to the graph of
For this reason, the high resistivity substrate of the structure with a P-N junction is more electrically insulating than that of the structure without a P-N junction.
The gain S21 corresponds to a cross-talk or noise measurement (called “cross-talk”) that reflects the ability of any components compared to other components to communicate through the substrate, thus representing the insulation performance capability of the substrate.
According to the graph of
According to the graph of
This confirms the fact that the substrate with high resistivity of the structure with a P-N junction is more electrically insulating than that of the structure without a P-N junction.
The graphs of
| Number | Date | Country | Kind |
|---|---|---|---|
| FR2000098 | Jan 2020 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/FR2021/050018 | 1/7/2021 | WO |
