Claims
- 1. A method for manufacturing solid electrolytic capacitor arrays, comprising steps of:
- (a) preparing a motherboard having an area from which a plurality of substrates can be cutout;
- (b) respectively forming a plurality of chips on said plurality of substrates included in said motherboard, each of said plurality of chips being formed by sintering metallic powder;
- (c) forming a plurality of solid electrolytic layers on surfaces of said plurality of chips, respectively, in a manner that each of said plurality of solid electrolytic layers is electrically insulated from said metallic powder, said plurality of solid electrolytic layers being independent from each other;
- (d) forming a covering resin layer which covers said plurality of chips in a manner that portions of said plurality of solid electrolytic layers are exposed;
- (e) forming at least one cathode electrode on said covering resin layer, said cathode electrode being electrically connected to each of said plurality of solid electrolytic layers;
- (f) forming at least one anode electrode on a lower surface of said motherboard, said anode electrode being electrically connected to said metallic powder of each of said plurality of chips; and
- (g) cutting-out said plurality of substrates from said motherboard.
- 2. A manufacturing method according to claim 1, wherein said step (b) includes (b-1) arranging a frame in which a plurality of filling spaces are respectively formed on said plurality of substrates on said motherboard; (b-2) filling said metallic powder in each of said plurality of filling spaces; (b-3) removing said frame; and (b-4) sintering filled metallic powder.
- 3. A manufacturing method according to claim 2, said step (a) includes (a-1) preparing a motherboard having an electrical conductivity in at least a thickness direction, said method further comprising, prior to said step (b), steps of (f) forming an insulation layer on which a plurality of contact holes are formed at positions each corresponding to each of said plurality of substrates on said motherboard, and (i) forming a plurality of contact layers on said insulation layer, which being connected to said plurality of substrates via said contact holes, respectively, and in said step (b-2), said metallic powder are filled on said plurality of contact layers.
- 4. A manufacturing method according to claim 3, wherein said step (i) includes steps of (i-1) forming a plurality of diffusion preventing layers on said plurality of substrates prior to forming of said plurality of contact layers, and (i-2) forming said plurality of contact layers being made of metallic material on said plurality of diffusion preventing layers.
- 5. A manufacturing method according to claim 2, wherein said step (a) includes a step (a-1) preparing a motherboard on which a filling recess portion is formed at a position equal to each of said plurality of substrates, and in said step (b-2), said metallic powder is filled in said filling recess portion and said filling space.
- 6. A manufacturing method according to claim 5, wherein said step (a-1) includes a step (a-11) preparing a motherboard in which a throughhole is formed at a position equal to each of said plurality of substrates, and said step (b-2) includes steps of (b-21) sealing a lower portion of said throughhole by a sheet, (b-22) filling said metallic powder in said throughhole and said filling space, and (b-23) removing said sheet, and in said step (f) said anode electrode is formed in a manner that said anode electrode is directly connected to said plurality of chips which are exposed at said lower surface of said plurality of throughholes.
- 7. A manufacturing method according to claim 6, wherein in said step (a) a motherboard made of insulative material is prepared.
- 8. A manufacturing method according to claim 6, wherein in said step (a) a motherboard having an electrical conductivity in at least a thickness direction is prepared.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-230749 |
Aug 1996 |
JPX |
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CROSS REFERENCE TO RELATED APPLICATIONS
This application is a Divisional application of U.S. application Ser. No. 08/920,517, filed on Aug. 29, 1997 now U.S. Pat. No. 5,926,363.
US Referenced Citations (3)
Foreign Referenced Citations (3)
Number |
Date |
Country |
4-3406 |
Jan 1992 |
JPX |
6-20891 |
Apr 1993 |
JPX |
405299311A |
Nov 1993 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
920517 |
Aug 1997 |
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