BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a process chart to explain essential portion of Embodiment 1 of a process for manufacturing a first substrate, which constitutes a liquid crystal display panel according to the present invention;
FIG. 2 is a schematical drawing to explain an essential structure in the process shown in FIG. 1;
FIG. 3 is a schematical drawing to explain an essential structure in the process shown in FIG. 1;
FIG. 4 is a schematical drawing to explain an essential structure in the process shown in FIG. 1;
FIG. 5 is a schematical drawing to explain an essential structure in the process shown in FIG. 1;
FIG. 6 is a schematical drawing to explain an essential structure in the process shown in FIG. 1;
FIG. 7 is a process chart continued from FIG. 1 to explain essential portion of Embodiment 1 of the process for manufacturing a first substrate (thin-film transistor substrate), which constitutes the liquid crystal display panel of the present invention;
FIG. 8 represents schematical drawings to explain essential structure in the process shown in FIG. 7;
FIG. 9 represents schematical drawings to explain essential structure in the process shown in FIG. 7;
FIG. 10 represents schematical drawings to explain essential structure in the process shown in FIG. 7;
FIG. 11 represents schematical drawings to explain essential structure in the process shown in FIG. 7;
FIG. 12 represents schematical drawings to explain essential structure in the process shown in FIG. 7;
FIG. 13 is a process comparison chart to explain the effects of the present invention;
FIG. 14 is another process comparison chart to explain the effects of the present invention;
FIG. 15 represents diagrams to explain equivalent circuit of an active matrix type liquid crystal display system;
FIG. 16 is a schematical drawing to explain an example of approximate arrangement of a pixel in a typical longitudinal electric field type (the so-called TN type) liquid crystal display system; and
FIG. 17 is a schematical drawing to explain an example of arrangement of a pixel in the liquid crystal display panel described in connection with FIG. 16 and an example of approximate arrangement of a thin-film transistor, which constitutes the pixel.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Detailed description will be given below on the preferred embodiment of the invention referring to the attached drawings.
Embodiment 1
FIG. 1 is a process chart to explain essential portion of Embodiment 1 of a process for manufacturing a first substrate (thin-film transistor substrate), which makes up a liquid crystal display panel of the present invention. It is a process chart to show the processes from the formation of a gate to the formation of an active layer island. The formation of the gate includes the formation of a gate line and a gate electrode. In Embodiment 1, the gate electrode is prepared by photolithographic process, and the active layer island is prepared by patterning process using a source-drain electrode, which is prepared by direct drawing of an electroconductive ink, as an etching mask.
FIG. 2 to FIG. 6 each represents a drawing of an essential structure in the process shown in FIG. 1. FIG. 4 is a cross-sectional view along the line A-A′ in FIG. 3, and FIG. 6 is a cross-sectional view along the line B-B′ in FIG. 5. In the following, description will be given on the process of FIG. 1 by referring to FIG. 2 to FIG. 6. In the formation of a gate in FIG. 1 (a), a metal for forming the gate (chromium, aluminum, copper, etc.) is sputtered, and a metal thin-film is deposited (P-1). On this metal thin-film, a photosensitive resist is coated, and a gate pattern of resist is formed by light exposure using a light exposure mask and development process (P-2). Etching is performed on the metal exposed from the resist, and only the portion covered by the photosensitive resist is kept untouched (P-3). The photosensitive resist is removed off and rinsed, and a gate (gate line and gate electrode) is prepared (P-4).
In the process for forming the active layer island and the source-drain electrode as shown in FIG. 1 (b), after the formation of the gate, on upper layer of a gate line GL and a gate electrode GT as shown in the plan view of FIG. 2, a gate insulator film GI, a silicon semiconductor layer SI, and an n+ silicon layer NS which is to be turned to a contact layer is deposited in this order by CVD method (3-layer CVD method) (P-5). On this upper layer, a source electrode material (source-drain electrode and data line material) and an ink (a first electroconductive ink) are applied by the ink jet direct drawing, and source direct drawing patterns DLA, SD1A and SD2A are prepared (P-6) as shown in FIG. 3(a). This is given as source direct drawing process in FIG. 1 (b).
Further, the source direct drawing pattern is turned to a continuous conductive film including a channel region of the thin-film transistor. On it, a transparent conductive film preferably made of ITO is applied by the ink jet direct drawing, and a cap layer CAP is formed (see FIG. 3 (b) and FIG. 4). In this case, the cap layer CAP is also coated on the contact layer NS of the channel region. Using the source-drain electrode and the channel region where the cap layer CAP is formed by the ink jet direct drawing as a mask, etching is performed on the contact layer (n+ silicon layer). Next, etching is performed on the silicon semiconductor layer SI, and an active island is formed (P-7) (see FIG. 5 and FIG. 6).
As a first electroconductive ink, low-resistance metal particles such as silver particles or copper particles are dispersed in a solvent and used. As a second electroconductive ink, transparent electroconductive particles or metal particles are dispersed in a solvent and used. As the low-resistance metal particles contained in the first electroconductive ink, silver particles or copper particle or mixture of these particles are preferably used. As the transparent conductive particles in the second electroconductive ink, metal oxide particles such as ITO (indium tin oxide) or IZO (indium zinc oxide) or IZTO are used. As the metal particles, nickel particles may be used.
FIG. 7 is a process chart continued from FIG. 1 to explain essential portion of Embodiment 1 in the process for manufacturing the first substrate (thin-film transistor substrate), which constitutes the liquid crystal display panel of the invention. This is a process chart from the formation of an interlayer insulator film and a contact hole to the formation of a gap of pixel electrode and channel.
FIG. 8 to FIG. 12 each represents drawings in the process of FIG. 7. Now, referring to FIG. 8 to FIG. 12, description will be given on the process of FIG. 7.
In FIG. 7 (a), an interlayer insulator film is prepared to cover the active layer island, which has been formed by etching using the source-drain electrode with the cap layer CAP on it and the channel region as a mask (P-8). The photosensitive resist is coated on this interlayer insulator film. Light exposure is performed by using a light exposure mask, and the interlayer insulator film on the cap layer of the source-drain electrode of the active layer island is solubilized (P-9). After the development process and the etching of this portion (P-10), the cap layer of the source-drain electrode is exposed (see FIG. 8).
FIG. 8 (a) is a plan view of an essential portion including the source-drain electrode formed by the process (P-10) of FIG. 7. FIG. 8 (b) is a cross-sectional view along the line C-C′ of the data line DL shown in FIG. 8 (a). FIG. 8 (c) is a cross-sectional view along the line D-D′ of the thin-film transistor shown in FIG. 8 (a). By the process (P-10) of FIG. 7, a cap layer CAP of the source-drain electrode is exposed. The other portion is covered by the interlayer insulator film INS. However, as shown in FIG. 9 and FIG. 10, the terminal region (FIG. 9) of the data line DL and the terminal region (FIG. 10) of the gate line GL are also processed by the photolithographic process and by the etching at the same time so that the cap layer CAP will be exposed.
Next, the pixel and gap forming process in FIG. 7 (b) includes the formation of a pixel electrode and a process to separate and fabricate source electrode and drain electrode. First, after the process (P-10) shown in FIG. 7, ITO is sputtered on the front surface (P-11). IZO, IZTO, etc. may be used instead of ITO. The photosensitive resist RG is coated on it as shown in FIG. 11 (a), and photolithographic process is performed in order to expose ITO of the data line, the gate line and the channel region (P-12). In FIG. 11 (b), a cross-section along the line E-E′ in FIG. 11 (a) is shown, and a cross-section along the line F-F′ in FIG. 11 (a) is shown in FIG. 11 (c).
ITO on the exposed portion is etched (P-13), and the cap layer CAP on the channel region is removed. When a nickel film is used as a cap layer on the cap layer, the data line terminal and the gate line terminal, etching is performed on these portions (P-14). As a result, ITO on the channel region is separated to a source electrode SD1 and a drain electrode SD2. In this case, ITO as a pixel electrode is separated in the pixel region. This pixel electrode is integrated with the source electrode SD1. Then, etching is performed on the contact layer NS, and a gap is formed (P-15). By removing the photosensitive resist off, the thin-film transistor is completed. This condition is shown in FIG. 12. In this case, a gap (distance) “d” is a gap of the cap layer CAP, and this is considerably narrower than a gap I“D” between the source electrode SD1A and the drain electrode SD2A prepared by the ink jet direct drawing as shown in FIG. 4. For instance, the gap D is 10 μm or more in width while the gap “d” can be set to 4 μm or less in width. This makes it possible to manufacture thin-film transistor at high speed and to have the display with high precision.
FIG. 13 is a process comparison chart to explain the effects of the present invention. In FIG. 13, a process A to show the prior art and a process B to show the present invention are the same in the gate forming process, the interlayer insulator film and the hole forming process, while these are different in the process for forming the active layer and the source-drain (S-D) and the pixel forming process. In the gate forming process in the process A and the process B, the gate line and the gate electrode are prepared in the order of: gate metal sputtering→photolithographic process→metal etching→removing off and rinsing of resist.
In the process A, the process for forming the active layer island and the source-drain (S-D) are performed in the order of: 3-layer CVD→photolithographic process→contact layer etching→removing off and rinsing of resist→sputtering of source metal→photolithographic process→metal etching→gap etching→removing off and rinsing of resist. Also, in the process for forming the interlayer insulator film and the hole, a contact hole is prepared by the processes in the order of: depositing of interlayer insulator film→photolithographic process→etching. In the pixel forming process, the processes are performed in the order of: Sputtering of ITO→photolithographic process→etching→removing off and rinsing of resist.
On the other hand, in the process B of the present invention, the processes for forming the island S-D after the gate forming process as described above are performed in the order of: 3-layer CVD→ink jet direct drawing of the source→etching of contact layer. In the pixel forming process after the interlayer insulator film forming and the hole forming process, the processes are performed in the order of: Sputtering of ITO→photolithographic process→etching→gap etching→removing off and rinsing of resist.
When the process A of the prior art and the process B of the present invention as shown in FIG. 13 are compared with each other, the photolithographic process is not adopted in the process for forming island and S-D in the process B. As a result, the number of light exposure masks can be reduced, and the liquid crystal display system can be manufactured at lower cost.
FIG. 14 is another process comparison chart to explain the effects of the present invention. The process C of the prior art and the process B of the present invention are the same in the gate forming process and in the process for forming the interlayer insulator film and hole, while the processes are different from each other in the process for forming the active layer island and the source-drain (S-D) and in the pixel forming process. Similarly to the process shown in FIG. 13, in the gate forming process in the process C and the process B, the gate line and the gate electrode are prepared in the order of: gate metal sputtering→photolithographic process→metal etching→removing off and rinsing of resist.
In the process C, the process for forming the active layer island and source-drain (S-D) are performed in the order of: 3-layer CVD→source metal sputtering→photolithographic process→metal etching→contact layer etching→ashing→metal etching→gap etching→removing off and rinsing of resist. Also, in the process for forming the interlayer insulator film and the hole, the contact hole as required can be prepared in the order of: depositing the interlayer insulator film→photolithographic process→etching. In the pixel forming process, the processes are performed in the order of: Sputtering of ITO→photolithographic process→etching→removing off and rinsing of resist.
On the other hand, in the process B of the present invention, similarly to the case shown in FIG. 13, the process for forming island and S-D is performed in the order of: 3-layer CVD→ink jet direct drawing of source→contact layer etching. In the pixel forming process after the process for forming the interlayer insulator film and hole, the processes are performed in the order of: sputtering of ITO→photolithographic process→etching→gap etching→removing off and rinsing of resist.
When the process C of the prior art and the process B of the present invention as shown in FIG. 14 are compared with each other, the photolithographic process is not adopted in the process for forming island and S-D in the process B. As a result, the number of the light exposure masks can be reduced and the liquid crystal display system can be manufactured at lower cost.
FIG. 15 represents diagrams to explain equivalent circuit of an active matrix type liquid crystal display system. FIG. 15 (a) is a circuit diagram of an entire liquid crystal display panel, and FIG. 15 (b) is an enlarged view of a pixel region PXL shown in FIG. 15 (a). In FIG. 15 (a), a multiple of pixels PXLs are arranged in matrix form on a display panel PNL. Each pixel region PXL is selected by a gate line driving circuit GDR and is turned on according to a display data signal sent from a data line driving circuit DDR.
Specifically, to match the gate line GL selected by the gate line driving circuit GDR, display data (voltage) is supplied to the thin-film transistor TFT on the pixel PXL of the liquid crystal display panel PNL via the data line DL from the data line driving circuit DDR.
As shown in FIG. 15 (b), the thin-film transistor TFT, which makes up the pixel PXL, is disposed at an intersection of the gate line GL and the data line DL. The gate electrode GT of the thin-film transistor TFT is connected to the gate line GL, and the data line DL is connected to the drain electrode SD2 of the thin-film transistor TFT.
The source electrode SD1 of the thin-film transistor TFT is connected to the pixel electrode PX of the liquid crystal (element) LC. The liquid crystal LC is positioned between the pixel electrode PX and the common electrode CT and is driven by a data (voltage) supplied to the pixel electrode PX. An auxiliary capacity Ca to temporarily maintain the data is connected between the drain electrode SD2 and the auxiliary capacity line CL.
In the description as given above, the lines and the electrodes or island forming layers to be formed by direct drawing of the ink jet are dried after the ink is coated by the ink jet method. After baking, the thin-film is prepared.
Patent Application
20080062344
