The present invention relates to a method for manufacturing a liquid ejection head substrate and a method for manufacturing a liquid ejection head.
With the recent trend for faster printing by a liquid ejection head, the nozzles have gotten longer, and heat generation resistance elements, logic circuits, and power supply interconnections have increased in number, increasing the size of chips for the liquid ejection head. In order for such liquid ejection head chips getting larger in size to be as compact as possible, the heat generation elements, logic circuits, power supply interconnections, and the like have become finer in size. To provide such fine elements and interconnections on chips for a liquid ejection head, a semiconductor exposure apparatus is used to reduce a photomask having a fine pattern of electric circuits drawn thereon with a lens and print the pattern onto an element substrate. For these reasons, a high-resolution semiconductor exposure apparatus capable of microfabrication is needed.
However, there is no semiconductor exposure apparatus that achieves a high resolution and a wide field of view at the same time. Thus, in a case where the chip size does not fall within the field of view of the semiconductor exposure apparatus, split exposure technique is used, in which a pattern for a chip is split into a plurality of patterns, and a high-resolution semiconductor exposure apparatus is used to perform exposure, joining the patterns together.
Japanese Patent Laid-Open No. 2004-111802 describes a joint exposure technique which performs exposures joining a plurality of patterns together. More specifically, in the technique described, for an interconnection that does not straddle over a joint position between patterns, split exposure is performed using a reduction projection apparatus supporting microfabrication, and for an interconnection that straddles over a joint position, a single-shot exposure is performed by a reduction projection apparatus having a large exposure area.
In a case of using the method of Japanese Patent Laid-Open No. 2004-111802, on a liquid ejection head substrate where a liquid flow channel and an ejection function film including a plurality of heat generation element portions are formed without straddling over a joint position, the ejection function film and the liquid flow channel are formed by split exposure using a high-resolution semiconductor exposure apparatus. Split exposure enables high-resolution formation, but at the split exposure border, changes the relative relation between the center positions of the liquid flow channel and the ejection function film including the heat generation resistance element portions of heat generation resistance elements. As a result, there is a concern that distortion of the ejection direction may occur, degrading the quality of a printed image.
Thus, the present invention provides a method for manufacturing a liquid ejection head substrate and a method for manufacturing a liquid ejection head capable of reducing degradation of the quality of a printed image.
To this end, a method for manufacturing a liquid ejection head substrate of the present invention includes: forming a split pattern on a substrate by performing exposure in a split manner through a mask pattern; forming a single-shot pattern on the substrate by performing exposure in a single-shot manner through a mask pattern; and setting a first part and a second part to the substrate, the first part being required to have higher positional precision than the second pattern, the second part being required to have higher fabrication precision than the first part. For the first part, the single-shot pattern is formed by the forming a single-shot pattern, and for the second part, the split pattern is formed by the forming a split pattern.
The present invention can provide a method for manufacturing a liquid ejection head substrate and a method for manufacturing a liquid ejection head capable of reducing degradation of the quality of a printed image.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
A first embodiment of the present invention is described below with reference to the drawings.
In a semiconductor manufacturing process, by light exposure using a semiconductor exposure apparatus, a photomask having an electric circuit pattern drawn thereon is reduced with a lens, and the electric circuit pattern is printed on an element substrate. In the present embodiment, a chip relatively large in size (a large chip) is employed.
Exposure methods by a semiconductor exposure apparatus include a single-shot exposure method and a split exposure method. In the single-shot exposure method, a chip is exposed to light with a single shot. This method offers a low resolution, but has a wide field of view and therefore creates no joint portion in the pattern. Thus, the relative relation between the circuits in the pattern does not change. In the split exposure method, a chip is exposed to light in a split manner. This method offers a high resolution, but creates a joint portion in the pattern. Thus, at the joint portion, it is necessary to provide excess space for the width of interconnections and between the interconnections. Also, the center positions of patterns may be misaligned at the joint portion, which may cause a change in the relative relation between the patterns. Thus, the single-shot exposure method and the split exposure method have their advantages and disadvantages, and it is desirable to use them selectively according to the exposure locations.
Thus, in the present embodiment, each part of a pattern to be printed onto a chip is divided into a part required to have a more precise relative positional relation or not required to have high fabrication precision and a part required to have higher fabrication precision. With a first part being the part required to have a more precise (positionally precise) relative positional relation or not required to have high fabrication precision, the single-shot exposure method is employed for the first part. Then, with a second part being the part required to have higher fabrication precision, the split exposure method is employed for the second part. In the liquid ejection head substrate 8, the part required to have a more precise relative positional relation (the first part) is, for example, a heat generation resistance element portion or the like, and single-shot exposure is performed using a semiconductor exposure apparatus with a wide field of view. Meanwhile, the part required to have higher fabrication precision (the second part) is a logic circuit, a through-hole portion, and the like, and split exposure is performed using a high-resolution exposure apparatus with a small field of view. In this way, to form a substrate, a first part and a second part are set to the substrate, and single-shot exposure and split exposure are selectively used to form a pattern. Steps for manufacturing the liquid ejection head substrate 8 are described below in the order of the steps.
A description is given of the logic circuit formation step (a logic circuit formation process S001 in
First, in the transistor layer formation step, a transistor layer is formed. First of all, wells 20 are formed in the element substrate 1. A high-resolution semiconductor exposure apparatus may be used here, but with a large chip, the chip needs to be exposed to light in a split manner, requiring man-hours. Thus, in the step of forming the wells 20, a semiconductor exposure apparatus with a wide field of view is used to form a pattern (a single-shot pattern) with single-shot exposure. The wide field-of-view semiconductor exposure apparatus used here has a field of view of 52 mm×56 mm and is capable of exposing a large chip to light with a single shot. Also, an i-line with an ultraviolet wavelength of 365 nm is used for the light source, and the resolving power is ≤500 nm, providing a resolution high enough for the formation of the wells.
Next, an element isolation 18 is formed in the element isolation formation step (see
Next, in the gate electrode formation step, gate electrodes 23 are formed (see
Next, in the source and drain formation step, sources and drains 19 are formed (see
Next, in the interlayer insulation film formation step, an interlayer insulating film is formed. The interlayer insulation film is formed using plasma chemical vapor deposition (CVD). A reactive gas is put into plasma state to generate active radicals and ions, causing them to have a chemical reaction and be deposited on the target substrate, thereby forming a thin interlayer insulation film.
A transistor layer can be formed through the steps thus described.
After that, in the contact formation step, contacts 17 are formed (see
After that, in the logic interconnection formation step, the logic interconnections 16 are formed (see
Etching is performed using the signal interconnection pattern, and the signal interconnections are thereby formed. An interlayer insulation layer is formed on the signal interconnections. The interlayer insulation layer can be formed using plasma CVD. Next, the interlayer insulating film is etched using the through-hole mask pattern, and the through-holes 14 are formed by embedding a through-hole member in opening portions (see
In this way, the transistor layer, the contacts, and the logic interconnections are formed in the logic circuit formation step, which is the first step.
A description is now given of the power supply interconnection formation step (a power supply interconnection formation process S002 in
A description is now given of the ejection function film formation step (an ejection function film formation process S003 in
First, a heat storage layer 13 is formed. A SiO film is used as the heat storage layer 13. Next, through-hole portions for the heat generation resistance elements 2 are formed. Via the through-holes 14, a current is passed from the power supply interconnections 15 to the heat generation resistance elements 2 in the ejection function film. The virtual size of the heat generation resistance elements 2 contributing to bubble formation in the current direction is determined by the distance between the through-holes. Thus, variations in through-hole diameters result in variations in the virtual size of the heat generation resistance elements 2 contributing to bubble formation, consequently causing variations in bubble formation. Thus, for the formation of the through-hole portions for the heat generation resistance elements 2, the through-holes 14 are regarded as the second part (NO in S011 in
For the formation of the ejection function film and the liquid flow channel part to be described later in the fourth step, it is necessary to have a high resolution and to have a precise relative relation between the center positions of the heat generation resistance elements 2 and the liquid flow channel part. In a case where a mask pattern for heat generation resistance element portions is formed by split exposure, the relative relation between the center positions of the ejection function film and the liquid flow channel part changes at the split exposure border. As a result, distortion of the ejection direction may be occur. For this reason, in the present embodiment, the heat generation resistance elements 2 are regarded as the first part (YES in S011 in
Also, depending on the product, a mask pattern for the heat generation resistance element portions and other portions of the ejection function film can be formed by single-shot exposure of the wafer surface. By preparing exposure data taking distortion of the wafer surface into consideration, the distortion of the wafer surface can be corrected. Under the heat generation resistance elements 2, the heat storage layer 13 with heat retention and insulation properties is provided. On top of the heat generation resistance elements 2, a protective film 11 with passivation, insulation, and ink-resistance properties is provided. These films can be formed by sputtering or plasma CVD. A liquid ejection head substrate can be manufactured in this way.
The pattern for the through-hole portions for the heat generation resistance elements 2 in the liquid ejection head substrate 8 thus formed has less variations in the through-hole diameters because of the split exposure. Also, as shown in
Also, because the heat generation resistance element portions are formed by single-shot exposure of the chip, the relative relation between the center positions of the liquid flow channel part and the ejection function film including the heat generation resistance elements 2 does not change even with the split exposure border being located in between as shown in
A description is now given of the liquid flow channel formation step (a liquid flow channel formation process S004 in
For patterns formed in the steps in the liquid flow channel formation step, positions relative to the heat generation resistance elements are important. For example, for the formation of the ejection ports, it is necessary to have a high resolution and have a precise relative relation between the center positions of each heat generation resistance element and its corresponding ejection port. In a case where split exposure is performed to form the ejection ports, the relative relation between the center positions of the ejection ports and the ejection function film including the heat generation resistance elements changes at the split exposure border. As a result, distortion of the ejection direction may occur. Thus, the ejection ports are regarded as the first part (YES in S011 in
The liquid flow channels are formed using the mask pattern thus formed. Specifically, liquid supply channels for feeding a liquid from the surface of the substrate to each ejection port are formed. Next, a layer to be flow channels and bubble formation chambers is tented on the substrate. Photoresist is used as a tenting material. Further, a layer remaining as the liquid flow channel part is tented. Patterning is performed in the order of a lower layer and an upper layer, thereby forming the flow channels, the bubble formation chambers, and the ejection ports. A liquid ejection head can thus be manufactured.
By thus performing single-shot exposure to reduce misalignment of the liquid flow channels, clearance provided to prevent interference between the substrate circuit portion and the opening portions of the liquid flow channels can be reduced. This allows reduction of chip size and also increases liquid supply speed. Also, by preparing exposure data with distortion of the wafer surface taken into consideration, the distortion of the wafer surface can be corrected.
Liquid flow channels in a liquid ejection head formed by the above method are formed without changing their relative relation to the center position of the ejection function film including the heat generation resistance elements, as shown in
In this way, in the formation of the liquid ejection head substrate 8, the single-shot exposure method is employed for the first part, which is a part required to have a more precise relative positional relation or not required to have high fabrication precision, and the split exposure method is employed for the second part, which is a part required to have higher fabrication precision. Thus, a method for manufacturing a liquid ejection head substrate and a method for manufacturing a liquid ejection head capable of reducing degradation of the quality of a printed image can be provided.
A second embodiment of the present invention is described below with reference to the drawings. Since the basic configuration of the present embodiment is the same as that of the first embodiment, the following only describes characteristic configurations.
Also, in the ejection function film formation step (the ejection function film formation process S003 in
The liquid ejection head thus manufactured by the above manufacturing method has a continuous distribution of a misalignment of the relative positions between the ejection function film and the liquid flow channel part. Thus, a liquid ejection head less likely to have distortion of the ejection direction can be provided. Also, the separation of the power supply interconnections 15 allows usage of high power. The anti-cavitation film 10 can reduce cavitation impact and damage from ink to the heat generation resistance elements 2. Further, the adhesion layer can reduce peeling of the substrate and the liquid flow channel part. Consequently, a liquid ejection head reliable over a long period of time can be provided.
A third embodiment of the present invention is described below with reference to the drawings. Since the basic configuration of the present embodiment is the same as that of the first embodiment, the following only describes characteristic configurations.
The liquid ejection head thus manufactured by the above manufacturing method has a continuous distribution of a misalignment of the relative positions between the ejection function film and the liquid flow channel part. Thus, a liquid ejection head less likely to have distortion of the ejection direction can be provided. Also, with the ejection detection sensor film 12, an ejection status such as the position and amount of liquid on the ejection detection film can be detected. Consequently, a liquid ejection head highly reliable in terms of print quality can be provided.
As a comparative example, a mask pattern used for an ejection function film including heat generation resistance element portions and a mask pattern used for the liquid flow channel part including ejection ports are formed using split exposure. At the split exposure border, the liquid ejection head thus manufactured by the above manufacturing method has a discontinuous distribution of a misalignment of the relative positions between the liquid flow channel part and the ejection function film including heat generation resistance element portions of the heat generation resistance elements 2. As a result, the ejection direction of the liquid ejected from the liquid ejection head is distorted.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2021-131994, filed Aug. 13, 2021, which is hereby incorporated by reference wherein in its entirety.
Number | Date | Country | Kind |
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2021-131994 | Aug 2021 | JP | national |
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Number | Date | Country |
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2003-145769 | May 2003 | JP |
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Entry |
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Office Action issued Jul. 4, 2023, in counterpart application JP 2021-131994 (3 pages). |
Number | Date | Country | |
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20230049764 A1 | Feb 2023 | US |