Method for manufacturing lower substrate of liquid crystal display device

Abstract

A method for improving the tapered angles of the insulating layer and the semiconductor layer of a lower substrate of a thin film transistor liquid crystal display device is disclosed. The method mainly applies an etching gas including a sulfur fluoride compound to etch the insulating layer. After etching, the tapered angle of the insulating layer is improved. Moreover, since the etching gas including a sulfur fluoride compound also results in lateral etching on the semiconductor layer, the step coverage of the subsequent process is improved, too. The method of the present invention can also be applied for manufacturing a multilayered thin film transistor containing a barrier layer, a semiconductor layer, and an insulating layer without delamination, breakage, or collapse. In addition, since the number of the used masks is reduced in the method of the present invention, the cost can be reduced and the process can be simplified.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-section view of a thin film transistor manufactured by four mask steps in the conventional method.

FIGS. 2( a) to 2(e) are schematic views of manufacturing an insulating layer, a semiconductor layer, a barrier layer, and a transparent electrode layer of a thin film transistor of the conventional manufacturing method.

FIGS. 3( a) to 3(h) are schematic views of fabricating a lower substrate of a TFT-LCD device of an embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENT

Embodiment 1

With reference to FIGS. 3(a) to 3(h), there are shown schematic views of fabricating a lower substrate of a liquid crystal display device of the present embodiment of the present invention. In the embodiment of the present invention, the lower substrate of a TFT-LCD device is prepared by four mask steps.

As shown in FIG. 3(a), a glass substrate 3 is prepared, and a first metal layer 31 is formed on the glass substrate 3. A pattern of the gate is defined by the first mask process and etching process. Preferably, the first metal layer 31 is composed of chromium alloy and molybdenum, and the structure can be a monolayer structure or a multilayered structure (not shown).

Then, as shown in FIG. 3(b), an insulating layer 32, a semiconductor layer 33, an ohmic contact layer 34, and a barrier layer 35 are deposited over the patterned first metal layer 31; wherein the insulating layer 32 is silicon oxide, the semiconductor layer 33 is amorphous silicon, the ohmic contact layer 34 is N⁺ amorphous silicon, and the barrier layer 35 is molybdenum. The ohmic contact layer 34 of the embodiment can make the ohmic contact between the semiconductor layer 33 and the upper device layer well to enhance the electric property and the efficiency.

As shown in FIGS. 3(c) and 3(d), a transistor region A and an auxiliary capacitance region B on the substrate 3 are defined by the second mask process and etching process. If necessary, a terminal block region on the substrate of a LCD device can be defined.

In the second mask process and etching process of the present embodiment, as shown in FIG. 3(c), the barrier layer 35 is patterned by dry or wet etching first. In the present invention, conventional wet etching is used to pattern the barrier layer 35. Then, the ohmic contact layer 34 and the semiconductor layer 33 are etched by dry etching so as to form the structure as shown in FIG. 3(c).

As shown in FIG. 3(d), the subsequent process for etching the insulating layer 32 is performed by an etching gas comprising SF₆. After patterning the insulating layer 32 by dry etching, the tapered angle of the insulating layer is about 40°. Herein, the patterned ohmic contact layer 34 and the patterned semiconductor layer 33 are further etched in the horizontal direction (side-etched), so as to form a tapered angle of about 55°. Therefore, an ideal tapered angle is formed, resulting from a taper configuration constructed by the semiconductor layer 33 and the insulating layer 32, and thereby the adhesion of the following film is improved.

In the present embodiment, the ratio of the tapered angle of the insulating layer to that of the semiconductor is 0.7 to 1.5 by an etching gas comprising SF₆ with the ability of side-etching. In a more detailed description, the ratio of tapered angle of the insulating layer to that of the semiconductor is about 0.7.

In etching of the present embodiment, the insulating layer without being protected by photoresist would be etched thoroughly, wherein the insulating layer in the light-penetrating region of the substrate is also etched to enhance the light transmittance of the light-penetrating region.

In the present embodiment, the insulating layer 32 is also patterned by dry etching, so the ohmic contact layer 34, the semiconductor layer 33 and the insulating layer 32 can be patterned in the same machine to reduce the manufacturing cost and to inhibit the formation of manufacturing defects caused by changing the fabrication process.

In etching the insulating layer 32, the flow, the RF power and the pressure of a etching gas can affect the tapered angle of the insulating layer. For example, when the flow of the etching gas increases by 100 sccm (standard cubic centimeter per), the tapered angle of the insulating layer reduces by 0.5-1.0. Therefore, the process parameters of etching the insulating layer 32 can be regulated to achieve an optimal manufacturing condition.

As shown in FIG. 3(e), a transparent electrode layer 36 (e.g. indium-zinc oxide, indium-tin oxide, or indium-tin-zinc oxide), and a second metal layer 37 (e.g. molybdenum) are deposited over the substrate 3, the transistor region A, and the auxiliary capacitance region B.

As shown in FIG. 3(f), a source and a drain in the transistor region A is defined by the third mask process and etching process to establish the structure of the transistor region A and the structure of the auxiliary capacitance region B completely. Herein, a barrier layer 35 forms between the transparent electrode layer 36 and the semiconductor layer 33 to function as an adhesion layer. Therefore, the delamination and poor contact caused by the difference of film properties between the two layers are inhibited so as to afford a thin film transistor with improved electric property.

In order to protect the transistor region A from oxidation, as shown in FIGS. 3(g) and 3(h), a second insulating layer 38 is formed and then patterned by the forth mask process and etching process, and the second metal layer 37 in the light-penetrating region of the substrate is removed. Herein, the second insulating layer 38 can be a passivation, an overcoat or a multilayered combination thereof. In the present embodiment, the second insulating layer 38 is a passivation of silicon nitride.

In the present embodiment, four mask steps to reduce the manufacturing cost can fabricate the lower substrate of a TFT-LCD device. Furthermore, the insulating layer in the light-penetrating region of the substrate is etched thoroughly to enhance the light transmittance of the substrate.

Embodiment 2

In the present embodiment, the manufacturing process of a lower substrate of a TFT-LCD device is the same as that of Embodiment 1 using a four-stage mask process, except that the semiconductor layer is a multilayer structure and the etching condition of the insulating layer is modified.

The semiconductor layer of the present embodiment is a multilayered structure comprising a low-deposition-rate Si layer and a high-deposition-rate Si layer. The multilayer structure of the lower substrate is established by depositing a first metal layer, a first insulating layer, a low-deposition-rate Si layer, a high-deposition-rate Si layer, an ohmic contact layer, and a barrier layer in sequence over the substrate.

In the present embodiment, forming a high-deposition-rate Si layer can reduce the time of depositing a semiconductor layer and increase the efficiency of manufacturing a lower substrate. In addition, the high-deposition-rate Si layer can thicken the semiconductor layer and also be an etching stop layer to inhibit shorting between elements caused by over-etching and thereby forming defects.

Furthermore, in etching the insulating layer of the present embodiment, the etching gas mixture including SF₆ having the ability of etching the semiconductor layer laterally, and a gas for regulating the formation rate of fluorine atoms, a noble gas, a fluorine-containing etching gas, or a chlorine-containing etching gas, is used.

The etching gas can improve the tapered angle of the insulating layer and further control the quality of etching, such as etching rate and uniformity. In the present embodiment, the flow ratio of the SF₆ having the ability of etching the semiconductor layer laterally to the auxiliary etching gas can be regulated to about 10:1 so as to provide a tapered angle and quality of etching. In the present invention, the flow ratio of the sulfur fluoride compound to the auxiliary etching gas can be regulated to meet the requirement of manufacturing. Preferably, the range of ratio is 1:1 to 100:1 to improve the uniformity of the etched insulating layer. Accordingly, the tapered angle of the insulating layer of the present embodiment is improved to 10°-55°, and the ratio of tapered angles of the insulating layer to the semiconductor layer is controlled in a range of 0.3-1.1.

The auxiliary etching gas used in the embodiment and the function thereof are described as the following:

A gas regulating the formation rate of fluorine atoms (e.g. O₂) is used to react with SF₆ to increase or decrease the formation rate of fluorine atoms and thereby the tapered angle of the insulating layer is controlled. For example, the addition of oxygen would increase the formation rate of fluorine atoms. When the flow of oxygen increases by 100 sccm (standard cubic centimeter per minute), the tapered angle of the insulating layer decreases by 0.5° to 15°. Furthermore, the flow ratio of the sulfur fluoride compound (such as SF₆) to the auxiliary etching gas (O₂) is about 25:1. Undoubtedly, the condition is not limited to those. Preferably, the flow ratio is 1:1 to 50:1. More preferably, the flow ratio is 3:1 to 100:1.

A noble gas including Ar, He, or N₂ is used for regulating the pressure of a gas in the present invention. In the present embodiment, Ar is used as a regulating gas. The pressure of a gas for etching the insulating layer significantly affects the tapered angle of the insulating layer. When the pressure of the etching gas increases by 10 mTorr, the tapered angle of the insulating layer decreases by 0.5° to 10°. The flow ratio of the etching gas with the ability of side-etching (such as SF₆) to the auxiliary etching gas (Ar) is about 50:1. The condition is not limited to those. Preferably, the flow ratio is 1:1 to 100:1. More preferably, the flow ratio is 30:1 to 90:1.

A fluorine-containing etching gas including CF₄, CHF₃, or C₂F₆ is used for forming products on the surface of the film in etching to regulate the tapered angle of the insulating layer. In the step for etching the insulating layer, the auxiliary etching gas of CF₄ reacts with the surface of the insulating layer to form a carbonized polymer. When the flow of the fluorine-containing etching gas increases by 100 sccm, the tapered angle of the insulating layer decreases by 0.5° to 10°. In the present embodiment, the flow ratio of the sulfur fluoride compound (such as SF₆) to the auxiliary etching gas (CF₄) is about 80:1. The condition is not limited to those. Preferably, the flow ratio is 1:1 to 100:1. More preferably, the flow ratio is 30:1 to 90:1 to avoid too many products formed on the surface of the insulating layer to increase the tapered angle and decrease the rate of etching the insulating layer.

A chlorine-containing etching gas including Cl₂, BCl₃ or HCl is used for decreasing the rate of etching the insulating layer to thereby decrease the tapered angle. When the flow of the chlorine-containing etching gas increases by 100 sccm, the tapered angle of the insulating layer decreases by 0.5° to 30°. Because the decrease in the tapered angle of the insulating layer is larger, the ratio of tapered angles of the insulating layer to the semiconductor layer decreases to 0.3-0.8. In the present embodiment, the flow ratio of the sulfur fluoride compound (such as SF₆) to the auxiliary etching gas (Cl₂ or HCl) is about 80:1. The condition is not limited to those. Preferably, the flow ratio is 1:1 to 100:1. More preferably, the flow ratio is 30:1 to 90:1 to avoid the rate of etching the insulating layer too slow.

Embodiment 3

In the present embodiment, the manufacturing process of a lower substrate of a TFT-LCD device is the same as that of Embodiment 2 with a four-stage mask process, except that the semiconductor layer is a monolayer structure illustrated in Embodiment 1, and the others, such as the etching gas and the other layer structures of the transistor are similar to those in Embodiment 2.

Embodiment 4

In the present embodiment, the manufacturing process of a lower substrate of a TFT-LCD device is the same as that of Embodiment 2 with a four-stage mask process, except that a barrier layer is not formed in the structure of the transistor, and the others, such as the etching gas and the other layer structures of the transistor are similar to those in Embodiment 2.

According to the description illustrated above, the present invention can improve the tapered angles of the insulating layer and the semiconductor layer to 10° to 60°, while the tapered angle in the conventional art is around 90°. In addition, using a different etching gas and condition can control the tapered angle of the insulating layer of the present invention.

Thereby, in the present invention, the manufacturing method of a lower substrate of a TFT-LCD device can enhance the performance of the transistor, the process stability and the transmittance of the light-penetrating region. Furthermore, the manufacturing cost can be reduced by the simplification of mask process.

Although the present invention has been explained in relation to its embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.

Claims

1. A method for manufacturing a lower substrate of a liquid crystal display device, comprising: providing a substrate;forming a patterned first metal layer on the substrate;forming a first insulating layer, a semiconductor layer, and a barrier layer over the substrate, and patterning the barrier layer and the semiconductor layer by a mask to form a transistor region;etching the first insulating layer and the patterned semiconductor layer laterally by an etching gas comprising a sulfur fluoride compound to form a tapered angle of the first insulating layer, wherein the range of the tapered angle is 10° to 70°;forming a transparent electrode layer and a second metal layer over the transistor region and the substrate; anddefining a source and a drain in the transistor region, wherein the source and the drain individually contain the second metal layer without connecting to each other.

2. The method of claim 1, further comprising a step, forming a patterned second insulating layer in the transistor region after defining the source and the drain.

3. The method of claim 1, wherein the content of the sulfur fluoride compound of the etching gas is 40% or more.

4. The method of claim 1, wherein the sulfur fluoride compound is sulfur hexafluoride, sulfur tetrafluoride, sulfur pentafluoride or a combination thereof.

5. The method of claim 1, wherein the etching gas further comprises at least one auxiliary etching gas, and the auxiliary etching gas is O2, Ar, He, N2, CF4, CHF3, C2F6, Cl2, BCl3, or HCl.

6. The method of claim 5, wherein the flow ratio of the sulfur fluoride compound to the auxiliary etching gas of the etching gas is 1/1 to 100/1.

7. The method of claim 1, wherein the tapered angle of the first insulating layer is 10° to 60°.

8. The method of claim 1, wherein the transistor region comprises the first metal layer.

9. The method of claim 1, further forming an ohmic contact layer on the semiconductor layer after forming the semiconductor layer.

10. The method of claim 1, wherein the step for etching the first insulating layer and the patterned semiconductor layer laterally is performed by dry etching.

11. The method of claim 1, wherein the etched first insulating layer is the first insulating layer outside the transistor region.

12. The method of claim 1, wherein a tapered angle of the semiconductor layer is formed and the tapered angle is 10° to 70° after etching the first insulating layer.

13. The method of claim 1, wherein the ratio of tapered angles of the insulating layer to the semiconductor is 0.3 to 1.5.

14. A method for manufacturing a lower substrate of a liquid crystal display device, comprising the steps: providing a substrate;forming a patterned first metal layer on the substrate;forming a first insulating layer and a semiconductor layer over the substrate, and patterning the semiconductor layer by a mask to form a transistor region;etching the first insulating layer and the patterned semiconductor layer laterally by a etching gas including a sulfur fluoride compound to form a tapered angle of the first insulating layer, wherein the range of the tapered angle is 10° to 70°;forming a transparent electrode layer and a second metal layer over the transistor region and the substrate; anddefining a source and a drain in the transistor region, wherein the source and the drain individually contain the second metal layer without connecting to each other.

15. The method of claim 14, further comprising a step, forming a patterned second insulating layer in the transistor region after defining the source and the drain.

16. The method of claim 14, wherein the content of the sulfur fluoride compound of the etching gas is 40% or more.

17. The method of claim 14, wherein the sulfur fluoride compound is sulfur hexafluoride, sulfur tetrafluoride, sulfur pentafluoride or a combination thereof.

18. The method of claim 14, wherein the etching gas further comprises at least one auxiliary etching gas, and the auxiliary etching gas is O2, Ar, He, N2, CF4, CHF3, C2F6, Cl2, BCl3, or HCl.

19. The method of claim 18, wherein the flow ratio of the sulfur fluoride compound to the auxiliary etching gas of the etching gas is 1/1 to 100/1.

20. The method of claim 14, wherein the tapered angle of the first insulating layer is 10° to 60°.

21. The method of claim 14, wherein the transistor region comprises the first metal layer.

22. The method of claim 14, further forming an ohmic contact layer on the semiconductor layer after forming the semiconductor layer.

23. The method of claim 14, wherein the step for etching the first insulating layer and the patterned semiconductor layer laterally is performed by dry etching.

24. The method of claim 14, wherein the etched first insulating layer is the first insulating layer beyond the transistor region.

25. The method of claim 14, wherein a tapered angle of the semiconductor layer is formed and the tapered angle is 10° to 70° after etching the first insulating layer.

26. The method of claim 14, wherein the ratio of tapered angles of the insulating layer to the semiconductor is 0.3 to 1.5.