Patent Application
20240213409
The present invention relates to the general field of colour micro-displays. The invention relates to a method for manufacturing micro-LEDs. The invention also relates to a structure thus obtained. The invention is particularly interesting because it allows improving the emission uniformity and repeatability of micro-displays based on micro-LEDs, in particular GaN-type micro-LEDs. The invention finds applications in numerous industrial fields, and in particular in the field of colour micro-displays based on micro-LEDs.
Colour micro-displays comprise pixels formed by blue, green and red subpixels (RGB pixels). In the remainder of the description, these subpixels will be referred to more simply as pixel for conciseness.
The blue and green pixels may be manufactured from nitride materials and the red pixels from phosphide materials. Red pixels may also be obtained from nitride materials, for example, by growth over a substrate including porous GaN.
A micro-display of GaN-based light-emitting diodes (LED) includes an array of unitary micro-LEDs on a substrate comprising a CMOS circuit. One LED corresponds to one pixel. Each LED is connected to the CMOS circuit.
According to a conventional manufacturing method, a GaN epitaxy and an upper anode may be pixelated directly over the growth substrate (made of sapphire or of Si), an electrode (cathode) may be deposited (with or without contact with the n-GaN), then metal pads added by the microelectronics means to enable a transfer with interconnection of the substrate containing the pixels onto the CMOS control circuit. Removing the growth substrate and thinning the GaN allows adding electrical functions at the rear face (contact with the n-GaN if not carried out at the front face), as well as limiting the cross-talk between the pixels and adding optical functions on the light emission side (for example in the upper passivation layers).
Another method for manufacturing micro-LEDs consists in bonding a GaN epitaxy and an anode which are not pixelated directly over a silicon plate containing the CMOS circuit. Bonding is a metal bonding enabling the conduction of the electrical current (eutectic or direct bonding). Then, this CMOS circuit and GaN epitaxy set is thinned in order to be able to subsequently use conventional microelectronics processes. Afterwards, the epitaxy as well as the bonding layer are pixelated in order to individualise the micro-LEDs of the micro-display array. Each of the micro-LEDs could then be addressed by the CMOS circuit.
An upper electrode (cathode) enables contact between the n-GaN either by lateral contact with the n-GaN (for example made of aluminium) or by contact above the n-GaN layer with a conductive transparent layer, for example, made of indium-tin oxide (ITO). The optical index of this ITO layer is comprised between 1.9 and 2.1. Afterwards, an encapsulation layer is deposited above the GaN. The encapsulation layer is conventionally made based on SiN whose optical index is also comprised between 1.9 and 2.1. In turn, the optical index of GaN is about 2.4.
However, in these two previously-described methods for manufacturing arrays of micro-LEDs, a variation in the thickness (TTV: “total thickness variation”) of the GaN is introduced, not only at the wafer level but also wafer-by-wafer. These thickness variations result from both the thickness variations of the epitaxy but especially from the thinning processes or planarisation processes used in order to pull off the buffer layers of the epitaxy which have a thickness of several microns, because of the non-uniformities of the used processes. Yet, these thickness variations could result in a variation in the optical performances of the LED (luminance, angular emission, spectrum, etc.), in particular when the anode is a mirror, and the LED thus formed is of the resonant cavity type (emissive source in a Fabry-Perot resonator). A modification of the thickness of the GaN will modify the optical cavity formed between the anode, the GaN and the upper optical interface (ITO/SiN in the previous example), which modifies extraction (into SiN in the example) and consequently extraction in air.
In the case where micro-lens or meta-surface type devices are structured in the upper encapsulation layer in order to maximise the light extraction and/or in order to deflect the optical flux in a specific direction, the uniformity of the emission in this passivation layer is even greater.
Indeed, the efficiency of these devices depends on the angular emission in the passivation layer.
In the case where the encapsulation layer is not structured, the uniformity of the emission in air (or the control of the extraction in air) may be improved by introducing an anti-reflective layer at the passivation layer/air interface or by depositing a passivation layer with a large thickness (typically about ˜1 μm).
The addition of the anti-reflector over the encapsulation layer avoids a return of light back to the stack.
However, even with an anti-reflective layer, the uniformity of the emission in air will be good only if the emission in the encapsulation layer is uniform.
The uniformity of the emission in the SiN may be obtained by widening the emission spectrum of the LED (but this is not what is desired for this device type) or by thickening the n-GaN but this also tends to reduce the EQE.
However, this adds steps to the method or cannot be compatible with all devices which are increasingly miniaturised.
Indeed, the addition of thick layers will introduce optical interference phenomena (“cross talk”) (also referred to as optical crosstalk) between the pixels in miniaturised devices, by lateral guidance of the light in the dielectrics.
In parallel, studies on the n-GaN porosification are conducted. For example, it has been shown in the article by Lin et al. (‘InGaN resonant microcavity with n+-porous-GaN/p+-GaN tunnelling junction’ (IEEE Elec. Dev. Lett, vol. 42, NO. 11, 2021) or in the article by Mishkat-UI-Masabih et al. (‘Electrically injected nonpolar GaN-based VCSELs with lattice-matched nanoporous distributed Bragg Reflector mirrors’, Appl. Phys. Express 12, 036504, 2019) that it is possible to manufacture a resonant-cavity LED by positioning conductive Bragg mirrors based on porous GaN at the top and at the bottom of the structure. The porosification allows modifying the optical index of the GaN and improving the light-emitting properties of the resonant-cavity LED, in particular by obtaining Bragg mirrors with high reflectivity on either side of the optical cavity, but also a perfect control of the optical cavity thickness (1λ for example).
However, this method is hardly usable in the case of arrays of miniaturised LEDs. The thickness of the Bragg mirrors reaches several μm, which poses a form factor problem for the microelectronics integration process. Thus, the described devices have a side of several tens of micrometres. In addition, the epitaxed stack is particularly complex (because it contains an alternation of strongly doped and less doped layers), and induces an increase in the resistivity of the μLEDs (porous n-GaN generally being less conductive than non-porous n-GaN).
The present invention aims to provide a method overcoming the drawbacks of the prior art, and in particular allowing manufacturing a micro-LED having a uniform and repeatable emission despite the process variations.
For this purpose, the present invention provides a method for manufacturing micro-LEDs comprising at least the following steps:
The optical index neff of the porosified GaN layer depends on the volumetric concentration of the pores in the layer. It will be selected according to the materials of the conductive transparent oxide layer and/or of the encapsulation layer. The pore volumetric concentration may be determined based on the following approximate formula:
with p the pore volumetric concentration, nGaN the optical index of the non-porosified GaN, and nair the optical index of air.
For example, in order to obtain an effective index neff of 1.9, a pore concentration in the range of 45% will be selected.
Advantageously, the conductive transparent oxide layer is an indium-tin oxide layer and/or the encapsulation layer is made of SiN, SiO2 or SiON. Advantageously, the encapsulation layer has an optical index close to that of ITO. Preferably, the encapsulation layer is made of SiN.
The invention fundamentally differs from the prior art by the presence of a porosified GaN layer beneath and in contact with the conductive transparent oxide layer or by the presence of a porosified GaN layer beneath and in contact with the encapsulation layer.
The optical index of the GaN is modified by the porosification. The porosification is conducted such that the optical index of the porosified GaN layer is close to:
Since the indices of the porosified layer, of the TCO layer and of the encapsulation layer are close, reflections at these interfaces are minimised, making emission in the SiN independent of the variations in the thickness of the porous GaN.
Advantageously, the porous GaN layer has a porosity between 40% and 70% by volume so as to have an effective optical index close to 1.9 (i.e. close to the optical index of the upper layers) and thus minimise reflections between the porous GaN and these upper layers.
The porous GaN layer being arranged between the anode (lower electrode) and the cathode (upper electrode, herein the conductive transparent oxide layer), the porosity will not be too high so that this porosified layer could transport electrons. To preserve a conductive porous layer, it is possible to implement a localised differential doping of the n-GaN layer in order to preserve a non-porosified area at the pixel level.
The fine localisation of the GaN/porous GaN interface allows controlling the thickness of the cavity of the LED and thus positioning the reflection interface between the GaN and the porous GaN at a constructive interference position in order to maximise the light extraction. Thus, it is possible to reduce the thicknesses of the micro-LEDs by the pattern (“design”) of the epitaxy, by compacting as much as possible the p-GaN stack, the quantum wells and n-GaN to its minimum, advantageously between 250 and 500 nm, in order to maximise coupling of the optical power in the vertical mode rather than in the plane-guided modes. The extraction gains as well as the emission uniformity gains will be even greater as the GaN thickness is small.
Preferably, the GaN layers are formed by epitaxy.
The porosification is carried out by electrochemical anodisation. The electrochemical porosification has a selectivity according to the doping level. It acts only in the most n-doped areas (1019 at·cm−3 for example), defined in particular during epitaxy. The position of the porous areas is then finely controlled. Thus, the non-porosified GaN thickness will be constant irrespective of the thickness variations resulting from the method. The variations, introduced by the method for manufacturing the micro-LED, are transferred into the porous layer which allows absorbing the process variations. The porous layer is an optical extraction layer which is tolerant to thickness variations.
The pixelation may be done before or after transfer, the growth substrate should be removed, at least if it is opaque (case of Si).
Advantageously, the thickness of the strongly doped GaN layer is comprised between 100 nm and 500 nm, preferably between 200 and 500 nm. Thus, the GaN thickness is larger than the TTV introduced by the epitaxy and by the thinning processes (in the range of 200 nm).
An anti-reflective layer may be deposited over the encapsulation layer.
According to a first advantageous embodiment, the method is a method for making micro-LEDs by monolithic bonding of the epitaxy.
According to a variant of this first embodiment, step i) is advantageously carried out according to the following steps a) to c):
According to another variant of this first advantageous embodiment, the method may comprise, before step ii), a step during which the doping level of the strongly n-doped GaN layer is locally reduced, for example by implantation of helium or hydrogen ions, so as to have a first portion of the strongly n-doped GaN layer having a first conductivity and a second portion of the strongly doped GaN layer having a second conductivity, the first electrical conductivity being higher at least by a ten factor than the second electrical conductivity, whereby:
Thus, the doped GaN layer comprises doped areas and weakly doped areas, the weakly doped areas not being porosified during step ii). The doped GaN layer of the mesas obtained in step iii) comprises a non-porosified central portion and a porosified boundary.
Still according to this first advantageous embodiment, the method may comprise the following steps:
In these two variants, the injection is improved because only the periphery of the GaN layer is porosified. The non-porosified area at the centre of the pixel may be used for contact resumption.
According to a second advantageous embodiment, the method is a method for making micro-LEDs by chip flipping or hybrid bonding.
According to this second embodiment, the method may comprise the following successive steps:
Advantageously, the method further comprises at least one of the following steps:
The method may further comprise a step of depositing a dielectric over the sidewall of the mesas acting as a passivation layer of the defects created during etching of the mesas as well as the deposition of an electrically- and heat-conductive element, for example copper-based, in the space between the mesas, thereby creating the second metal electrode (cathode) which will be in contact with the N contact deposit made of ITO or using the lateral contact.
It is possible to reduce the thicknesses of the micro-LEDs, because the extraction gains as well as the emission stability gains will be even greater as the GaN thickness is small.
The invention also relates to a micro-LED structure obtained according to the previously-described method.
A micro-LED structure comprising a stack, the stack comprising at least one porosified strongly n-doped GaN layer, an n-doped GaN layer, quantum wells, a p-doped GaN layer and a first electrode, mesas being formed in the stack,
For example, the structure comprises a substrate of interest, the substrate of interest comprising a support substrate, a first electrode, a p-doped GaN layer, GaN/InGaN quantum wells, an n-doped GaN layer, a strongly doped GaN layer, mesas being formed in the substrate of interest. The mesas comprising the porosified strongly doped GaN layer, the doped GaN layer, the quantum wells, the p-doped GaN layer, the lower electrode and a portion of the support substrate. The mesas are covered with a second electrode formed by a conductive transparent oxide layer, preferably an indium-tin oxide layer, and/or with an encapsulation layer.
Advantageously, the strongly doped GaN layer of the mesas comprises a non-porosified central portion and a porosified boundary.
According to a first advantageous variant, the central portion is weakly doped.
According to a second advantageous variant, the central portion is strongly doped.
Advantageously, the porosified GaN layer has a thickness comprised between 100 and 500 nm, preferably between 300 and 500 nm.
Other features and advantages of the invention will appear from the following complementary description.
It goes without saying that this complementary description is given only as an illustration of the object of the invention and should in any event be interpreted as a limitation of this object.
The present invention will be better understood upon reading the description of embodiments given for merely indicative and non-limiting purposes with reference to the appended drawings, wherein:
The different parts shown in the figures are not necessarily plotted according to a uniform scale, to make the figures more readable.
The different possibilities (variants and embodiments) should be understood as not being mutually exclusive and can be combined with one another.
Furthermore, in the description hereinafter, terms that depend on the orientation, such as “top”, “bottom”, etc., of a structure apply while considering that the structure is oriented as illustrated in the figures.
Although this is in no way limiting, the invention finds applications in particular in the field of monochromatic micro-displays or colour micro-displays, and more particularly for LED manufacturing. However, it could be used in the photovoltaic or water electrolysis (“water splitting”) field since, firstly, InGaN absorbs throughout the visible spectrum and, secondly, its valence and conduction bands are around the water stability domain, the thermodynamic condition necessary for the water decomposition reaction. The invention may also be interesting for the manufacture of lasers emitting at long wavelengths.
The invention is described more particularly for monolithic-type integration by complete transfer of the layers, i.e. the porosification step is carried out after transfer (
However, it is also possible to carry out the porosification step on the growth substrate, manufacture the LED then perform a flip-chip type assembly or hybrid bonding on a substrate comprising an “ASIC”-type integrated circuit (“Application-Specific Integrated Circuit”). The porosification step is carried out after transfer, which allows achieving a relief during the growth (
The method is particularly interesting for manufacturing structures comprising porosified (Al,In,Ga)N/(Al,In,Ga)N mesas having in particular a pitch of less than 30 μm.
By (Al,In,Ga)N, it should be understood AlN, AlGaN, InGaN or GaN. Next, reference is made more particularly to porous GaN, but it is possible to have, for example, porous InGaN or AlGaN.
We will describe in more detail the micro-LED manufacturing method with reference to the appended
The micro-LED manufacturing method comprises the following steps:
According to a first alternative, the method may further comprise the following steps:
According to another alternative, the method may further comprise the following steps:
Thus, the contact of the second electrode 301 may be made on the upper face of the porosified GaN layer 104′, on the lateral face of the porosified GaN layer 104′ or on the lateral face of the doped GaN layer 105.
The upper face of the porosified GaN layer 104′ is in direct contact with the upper electrode 301 made of a conductive transparent oxide or in direct contact with the encapsulation layer 302. By “in direct contact”, it should be understood that there is no intermediate layer between the aforementioned layers.
The first stack provided in step a) comprises a base substrate 101 having, for example, a thickness ranging from 250 μm to 2 mm. The thickness depends on the nature of the base substrate 101 and on its dimensions. For example, for a base substrate made of sapphire with a 2-inch diameter, the thickness may be 350 μm. For a support layer made of sapphire with a 6-inch diameter, the thickness may be 1.3 mm. For a support layer made of silicon with a 200-mm diameter, the thickness may be 1 mm.
In the case of a base substrate 101 made of silicon, a buffer layer made of (Al,Ga)N is advantageously interposed between the substrate 101 and the nid-GaN layer 103. It consists of a buffer layer for growth.
The nid-GaN layer 103 is a non-intentionally doped (nid) layer in order not to be porosified. By non-intentionally doped GaN, it should be understood a concentration lower than 5×1017 at/cm3. For example, the layer 103 made of nid-GaN has a thickness ranging from 500 nm to 5 μm. Advantageously, its thickness is between 1 and 4 μm to absorb the stresses related to the lattice mismatch between the GaN and the underlying layers.
The strongly n-doped GaN layer 104 is deposited over the nid-GaN layer. By strongly doped GaN, it should be understood a concentration higher than 6×1018 at/cm3, preferably at least 8×1018 at/cm3, and possibly higher than 1019 at/cm3. It has a thickness comprised between 100 nm and 500 nm, preferably between 200 nm and 500 nm and even more preferably between 300 nm and 500 nm. This layer allows absorbing the TTVs due to the manufacturing process of the micro-LEDs. This layer is porosified during step d).
The strongly n-doped GaN layer 104 comprises two main faces (an upper face and a lower face) parallel or substantially parallel to one another and a lateral face.
The doped GaN layer 105 is formed over the strongly doped GaN layer 104. By doped GaN, it should be understood a concentration higher than 1018 at/cm3, preferably between 1×1018 at/cm3 and 5×1018 at/cm3. For example, the layer made of GaN has a thickness ranging from 100 nm to 1 μm. It must be sufficiently electrically conductive to be able to achieve a resumption of contact on this layer during the electrochemical anodising step. This electrically-conductive layer is electrically connected to the voltage or current generator. Advantageously, the quality of the material of the upper layer is ensured. The minimum thickness varies according to the doping level.
The n-doped GaN layer 105 comprises two main faces (an upper face and a lower face) parallel or substantially parallel to one another and a lateral face.
Next, an n-type doping is described, but it could consist of a p-type doping. The dopings could be inverted.
For example, the quantum wells 106 are GaN/InGaN wells.
For example, the p-doped layer 107 has a thickness comprised between 100 nm and 200 nm. For example, it may have a doping level of 1×1019·cm−3 and possibly of at least 1×1020·cm−3 in the case of an Mg doping.
The aforementioned different GaN layers as well as the quantum wells 106 are formed by epitaxy.
The first stack 100 may be a more complex stack and may contain, for example, one or more of the following elements: an AlGaN electron-blocking layer (EBL), a multilayer with different dopings to make porous mesas, etc.
During step b), the first stack (p side) is transferred onto a second stack comprising a support substrate 201 and a lower electrode 202 (or first electrode). The first electrode 108 is deposited over the first stack and then the whole is transferred onto the support substrate 201 covered with the metal layer 202.
Preferably, the support substrate 201 is a substrate comprising an ASIC-type integrated circuit, (“Application-Specific Integrated Circuit”). The ASIC circuit may comprise electronic components (transistor(s), capacitor(s), resistors, etc.) enabling the individual control/power supply of each micro-LED according to the colour expected for the pixel. The electronic components are made directly in the volume (or “bulk”) of the substrate.
The support substrate 201 may also be an array substrate of thin-film transistors (TFT), in particular to obtain larger direct-view displays.
Preferably, the substrate 201 is a silicon wafer.
The lower electrode 202 (or first electrode) covers the support substrate. It could also be made of ITO. For example, the lower electrode 202 is made of aluminium or silver. For example, it may have a thickness comprised between 40 and 200 nm.
During step c), the base substrate 101, the buffer layer 102 where appropriate, and the nid-GaN layer 103 are removed. For example, the base substrate 101 is removed by laser (also referred to as lift-off technique). The buffer layer 102 and the nid-GaN layer 103 may be removed by thinning. Thinning may be terminated at the nid layer 103/strongly doped GaN layer 104 interface. Preferably, thinning is terminated in the strongly doped GaN layer 104.
During step d), the strongly doped GaN layer 104 is partially or totally porosified. The higher the doping level, the greater the porosification at fixed potential will be. The choice is done according to the targeted optical index.
During step d), the structure and a counter-electrode (CE) are electrically connected to a voltage or current generator. The structure serves as a working electrode (WE). Next, it will be referred to as voltage generator, but it could consist of a current generator allowing applying a current between the device and the counter-electrode.
Contact is achieved on an electrically-conductive layer of the structure, preferably, on the doped GaN layer 105.
The counter-electrode is made of an electrically-conductive material, for example a metal such as platinum.
During step d), the electrodes are immersed in an electrolyte, also called electrolytic bath or electrolytic solution. The electrolyte may be acidic or basic. For example, the electrolyte is oxalic acid. It may also consist of KOH, HF, HNO3, NaNO3, or H2SO4 or a mixture thereof.
For example, the applied voltage may be comprised between 1 and 30V. Preferably, it is between 5 and 18V (for example between 5 and 15V), and even more preferably between 6 and 12V, for example between 8 and 10V. The voltage is selected according to the doping level of the different layers and the targeted porosity level. For example, it is applied for a duration ranging from a few seconds to several hours. Porosification is complete when there is no longer any current of the imposed potential. At this point, the entire doped structure has been porosified and the electrochemical reaction stops.
The electrochemical anodising step may be carried out under ultraviolet (UV) light.
Upon completion of the porosification step, the porosity level of the porosified GaN layer 104 is at least 10%. Preferably, it ranges from 10% to 80%, and even more preferably from 30% to 70%.
The largest dimension (the height) of the pores may vary from a few nanometres to a few micrometres. The smallest dimension (the diameter) may vary from a few nanometres to a hundred nanometres, in particular from 30 to 70 nm.
The obtained porosification (porosity level and pore size) depends on the doping of the layer and the parameters of the method (voltage applied, duration, nature and concentration of the electrolyte, chemical post-treatment or annealing).
The anodisation of the GaN layer 104 may be total. According to some variants described in more detail later on, the anodisation may be partial. In other words, one or more area(s) 110 of the strongly doped GaN layer are not porosified during step d). Each non-porosified area extends from the first main face to the second main face to form an electrical conduction path through the GaN layer. For example, the electrical conduction path may be in the form of a channel or a tube.
Thus, the electrical conduction is improved by selecting the position of the non-porosified areas. In addition, it is possible to act on the relief.
During step e), the mesas are formed. For example, structuring of the stack is carried out by photolithography.
Mesas, also referred to as elevations, are raised elements. They are obtained, for example, by etching a continuous layer or a plurality of stacked continuous layers, so as to leave only a certain number of “raised portions” of this layer or these layers. Etching is typically a plasma etching (or dry etching) process. The raised portions can be used to define pixels.
Preferably, the sidewalls of the mesas are perpendicular to this stack of layers.
For example, the surface of the mesas may be circular, hexagonal, square or rectangular.
The largest dimension of the surface of the mesas ranges from 500 nm to 500 μm, preferably from 1 to 10 μm and even more preferably from 3 to 5 μm. For example, the largest dimension of a circular surface is the diameter.
The thickness (or depth) of the mesas corresponds to the dimension of the mesa perpendicular to the underlying stack. The depth of the mesas ranges from 0.5 to 1 μm, preferably from 0.3 to 2 μm.
The spacing between two consecutive mesas ranges from 50 nm to 20 μm.
During step f), a second electrode 301 is deposited over the porosified layer 104′ (i.e. over the upper face of the porosified layer 104′). The second electrode is a conductive transparent oxide layer. It may consist of an indium-tin oxide layer (ITO), aluminium-doped zinc oxide (AZO), gallium zinc oxide (GZO) or SnO2. This layer covers the mesas. The conductive transparent oxide layer serves as an upper electrode or cathode.
After step f), it is possible to implement a step g) of depositing an encapsulation layer 302 over the conductive transparent oxide layer 301. For example, the encapsulation layer 302 is a layer made of SiN, SiO2 or SiON. It could also consist of a multilayer.
Structuring of the encapsulation layer 302 by micro-lenses may also be carried out.
It is also possible to deposit an anti-reflector 303 (i.e. an anti-reflective layer) over the encapsulation layer 302 (step h)).
Advantageously, the method comprises between step e) and step f), a step during which a planarising material or stack 304 is deposited between the mesas. The material or the stack may be conductive or insulator. Preferably, it includes copper. For example, the material is deposited by electrochemical deposition (ECD). Advantageously, a step of chemical-mechanical polishing (CMP) of the deposited material 304 is carried out.
We will now describe two variants for which the core of the strongly doped GaN layer of the pixels is not porosified. For example, the core represents 5% to 25% of the volume of the layer.
According to an advantageous variant, shown in
For example, the local decrease in the doping level of the strongly doped GaN layer 104 is achieved by implanting helium or hydrogen. The ion implantation step allows reducing the conductivity, deactivating the dopants initially in presence.
After the porosification step, it is possible to carry out a thermal annealing step to increase the conductivity of the area 110.
According to another advantageous variant, shown in
We have previously described variants implementing a porosification step after transfer (integration with monolithic bonding of the epitaxy).
We will not describe in more detail a variant where the porosification step is implemented before the transfer step (so-called flip-chip integration).
According to this other advantageous variant, shown in
The characteristics of the different layers, of the different elements described for this variant where the porosification step is implemented before the transfer step may be identical to the characteristics of the different layers, of the different elements described for the variant where the porosification step is implemented after the transfer step.
The obtained micro-LED structure comprises:
As mentioned before, the GaN layer 104′ of the mesas may be totally porosified or partially porosified.
Advantageously, the GaN layer 104′ of the mesas comprises a non-porosified central portion 110 and a porosified boundary.
The central portion may be weakly doped or strongly doped.
The approach is particularly interesting:
In any case, the uniformity of the emission in the encapsulation is found in the air thanks to a structuring that breaks the cavity effect, namely by addition of an anti-reflective layer which enables the light emitted in the encapsulation layer, in particular made of SiN, to pass directly into the air without interacting again with the stack of the structure.
In this first illustrative example, the studied LED stack successively comprises (
The simulation of the luminance at 0° (in the axis perpendicular to the plane of the structure) in the SiN according to the n-GaN thickness (
In this example, the studied LED stack successively comprises (
The simulation of the luminance at 0° in SiN according to the porous GaN thickness (
In this first illustrative example, the studied LED stack successively comprises (
The simulation of the luminance at 0° in air, located above the layer 303, according to the n-GaN thickness (
In this example, the studied LED stack successively comprises (
The non-porosified GaN thickness is selected so as to be at a maximum extraction.
The simulation of the luminance at 0° in the air, located above the layer 303, according to the porous GaN thickness (
In addition, the simulation of the luminance in air according to the observation angle for different porous GaN thicknesses (
The 2D simulation of the external quantum efficiency or EQE (in air) of a micro-LED having mesas with a size of about 1 μm according to the GaN thickness has also been studied (
It is interesting to note that the smaller the GaN thicknesses, the higher the EQE will be and the greater the oscillations according to the GaN thickness will be. The oscillation effects might be even greater as the angular space will be reduced, for example if the considered emission is between 0 and 18.5° in the axis perpendicular to the plane of the structure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 22 14156 | Dec 2022 | FR | national |
