Patent Application
20050074929
The present invention relates to a method of manufacturing a complementary MOS semiconductor device having a resistor circuit, for which low voltage operation, low power consumption, and high drive power are required. In particular, the present invention relates to a power management semiconductor device such as a voltage detector (hereinafter referred to as a VD), a voltage regulator (hereinafter referred to as a VR), or a switching regulator (hereinafter referred to as an SWR), or an analog semiconductor device such as an operational amplifier or a comparator.
Conventionally, many kinds of complementary MOS semiconductor devices having a resistor circuit using a resistor made of polycrystalline silicon or the like are used.
In the complementary MOS (CMOS) semiconductor device having the resistor circuit, the N+-type polycrystalline silicon is often used for the gate electrode in view of a polarity thereof because of ease and stability of the manufacturing operation. In this case, from a relationship of work functions between the gate electrode and the semiconductor substrate (well), the NMOS transistor becomes a surface channel type NMOS transistor. On the other hand, in the case of the PMOS transistor, a threshold voltage becomes about −1 V also from the relationship of work functions between the gate electrode and the semiconductor substrate. Thus, when impurity implantation is conducted for reducing the threshold voltage, the PMOS transistor becomes a buried channel type PMOS transistor in which a channel is formed in the inner portion of the substrate, which is slightly deeper than the surface thereof. The buried channel type transistor has an advantage of high mobility because a carrier is transferred through the inner portion of the substrate. However, when the threshold voltage is reduced, a subthreshold characteristic is greatly deteriorated, thereby increasing a leak current. Thus, it is difficult for the PMOS transistor to reduce a voltage and shorten a channel as compared with the NMOS transistor.
Also, as a structure capable of reducing a voltage in both the NMOS transistor and the PMOS transistor, there is a homopolar gate structure in which the polarity of the gate electrode is set to be equal to that of the transistor. According to this structure, N+-type polycrystalline silicon is used for the gate electrode of the NMOS transistor and P+-type polycrystalline silicon is used for the gate electrode of the PMOS transistor. Thus, each transistor becomes a surface channel type transistor. As a result, a leak current can be suppressed and a voltage can be reduced. However, there are the following problems in costs and characteristics. That is, when the gate electrodes having different polarities are formed, the number of manufacturing steps is thereby increased and increases in a manufacturing cost and a manufacturing period are caused. Further, with respect to an inverter circuit as a most fundamental circuit element, generally, in order to improve area efficiency, the layout for the gate electrodes of the NMOS transistor and the PMOS transistor is made such that a connection through metal is avoided and a piece of polycrystalline silicon which is two-dimensionally continued from the NMOS transistor to the PMOS transistor or a polycide structure composed of a laminate of a polycrystalline silicon film and a high melting point metallic silicide film is used. However, when the gate electrode is made of polycrystalline silicon as a single layer, it is impractical because of a high impedance of a PN junction in the polycrystalline silicon. Also, when the gate electrode has a polycide structure, an N-type impurity and a P-type impurity each are diffused to respective gate electrodes having an inverse conductivity type through high melting point metallic silicide films at high speed during heat treatment in manufacturing steps. As a result, a work function is changed and a threshold voltage is unstable.
In order to solve the above-mentioned problems, the present invention adopts the following measures. (1) A method of manufacturing a semiconductor device including the steps of: forming an element isolation insulating film on a semiconductor substrate by thermal oxidation; forming a gate insulating film by thermal oxidation; depositing a first polycrystalline silicon film at a thickness of 500 Å to 2500 Å on the gate insulating film; doping the first polycrystalline silicon film with an impurity such that a concentration of the impurity is 1×1018 atoms/cm3 or higher to make a conductivity type of the first polycrystalline silicon film a P-type; depositing a high melting point metallic silicide film having a thickness of 500 Å to 2500 Å on the first polycrystalline silicon film having the P-type; depositing an insulating film having a thickness of 500 Å to 3000 Å on the high melting point metallic silicide film; etching the first polycrystalline silicon film having the P-type, the high melting point metallic silicide film, and the insulating film to form a gate electrode; depositing a second polycrystalline silicon film having a thickness of 500 Å to 2500 Å on the element isolation insulating film; doping an entire region of the second polycrystalline silicon film or a first region of the second polycrystalline silicon film with a first conductivity type impurity at a concentration of 1×1014 to 9×1018 atoms/cm3; doping a second region of the second polycrystalline silicon film with a second conductivity type impurity at a concentration of 1×1014 to 9×1018 atoms/cm3; etching the second polycrystalline silicon film to form a resistor composed of the second polycrystalline silicon film; doping the low concentration diffusion region of the first conductivity type MOS transistor with the first conductivity type impurity at a concentration of 1×1016 to 1×1018 atoms/cm3; doping the low concentration diffusion region of the second conductivity type MOS transistor with the second conductivity type impurity at a concentration of 1×1016 to 1×1018 atoms/cm3; doping a portion or an entire region of the first region of the second polycrystalline silicon film with the first conductivity type impurity at a concentration of 1×1019 atoms/cm3 or higher; performing heat treatment so that the low concentration diffusion region of the first conductivity type MOS transistor and the low concentration diffusion region of the second conductivity type MOS transistor have a region overlapped with the gate electrode; doping a portion or an entire region of the first region of the second polycrystalline silicon film with the first conductivity type impurity at a concentration of 1×1019 atoms/cm3 or higher; doping a portion or an entire region of the second region of the second polycrystalline silicon film with the second conductivity type impurity at a concentration of 1×1019 atoms/cm3 or higher; forming an intermediate insulating film over the semiconductor substrate; forming a contact hole in the intermediate insulating film over the semiconductor substrate; and providing a metallic wiring in the contact hole.
(2) A method of manufacturing a semiconductor device, characterized in that an impurity introducing method for the first polycrystalline silicon film is for ion implantation of boron.
(3) A method of manufacturing a semiconductor device, characterized in that the impurity introducing method for the first polycrystalline silicon film is for ion implantation of BF2.
(4) A method of manufacturing a semiconductor device, characterized in that the impurity introducing method for the first polycrystalline silicon film is a doped-CVD method of depositing the first polycrystalline silicon film while the impurity is mixed thereinto.
(5) A method of manufacturing a semiconductor device, characterized in that the insulating film deposited on the high melting point metallic silicide film is composed of an oxide film.
(6) A method of manufacturing a semiconductor device, characterized in that the insulating film deposited on the high melting point metallic silicide film is composed of a nitride film.
(7) A method of manufacturing a semiconductor device, characterized in that the insulating film deposited on the high melting point metallic silicide film is composed of a laminate of an oxide film, a nitride film, and another oxide film different from the oxide film.
(8) A method of manufacturing a semiconductor device, characterized in that the step of doping the low concentration diffusion region of the first conductivity type MOS transistor with the first conductivity type impurity at a concentration of 1×1016 to 1×1018 atoms/cm3 and the step of doping the first conductivity type impurity to the portion and the entire region of the first region of the second polycrystalline silicon film are simultaneously conducted, and the step of doping the low concentration diffusion region of the second conductivity type MOS transistor with the second conductivity type impurity at a concentration of 1×1016 to 1×1018 atoms/cm3 and the step of doping the second conductivity type impurity to the portion and the entire region of the second region of the second polycrystalline silicon film are simultaneously conducted.
(9) A method of manufacturing a semiconductor device, characterized in that doping of the first conductivity type impurity at a concentration of 1×1019 atoms/cm3 or higher to the portion and the entire region of the first region of the second polycrystalline silicon film is performed simultaneously with doping to a diffusion region of the first conductivity type MOS transistor, and doping of the second conductivity type impurity at a concentration of 1×1019 atoms/cm3 or higher to the portion and the entire region of the second region of the second polycrystalline silicon film is performed simultaneously with doping to a diffusion region of the second conductivity type MOS transistor.
Hereinafter, an embodiment of the present invention will be described in detail using the drawings.
In this embodiment, an N-type well diffusion layer region 102 is formed in a P-type silicon semiconductor substrate 101 and has a conductivity type opposite to the substrate. Further, impurity diffusion layers each having a conductivity type opposite to the silicon semiconductor substrate 101 are formed therein for an N-type MOS transistor 114. Impurity diffusion layers each having a conductivity type opposite to the N-type well diffusion layer region 102 are formed therein for a P-type MOS transistor 115. Each of the transistors is composed of a gate insulating film 105 and a gate electrode in addition to the impurity diffusion layer. The gate electrode has a laminate polycide structure of a P+-type polycrystalline silicon film 107 and a high melting point metallic silicide film 112. An oxide insulating film 113 is deposited on the gate electrode as a mask member therefor. Here, a nitride film may be used as the mask member for the gate electrode. In addition, the P-type silicon semiconductor substrate is used here. However, a P-type well diffusion layer may be formed in an N-type silicon substrate so as to construct a CMOS semiconductor device thereto.
Also, in this embodiment, a polycrystalline silicon resistor 116 which is made from a second polycrystalline silicon film and has an N-type as a first conductivity type and a polycrystalline silicon resistor 117 which is made from the second polycrystalline silicon film and has a P-type as a second conductivity type are formed on a field insulating film 106. Here, the polycrystalline silicon film 107 as a portion of the gate electrode in the CMOS transistor and the polycrystalline silicon resistors 116 and 117 are formed in separate steps and have different film thicknesses. The polycrystalline silicon resistors are formed to be thinner than the gate electrode. For example, the film thickness of the gate electrode is about 2000 Å to 6000 Å. On the other hand, the film thickness of each resistor is 500 Å to 2500 Å. When the polycrystalline silicon resistors are thin, a high sheet resistance value can be set and a temperature characteristic becomes preferable. Thus, the accuracy of resistor can be further improved.
The N-type polycrystalline silicon resistor 116 includes a high resistance region 110 and high concentration impurity regions 108 which are provided in both end portions of the resistor such that they are in sufficient contact with wiring members. The impurity concentration of the high resistance region 110 is controlled by ion implantation, thereby forming the resistors each having a desirable resistance value. Similarly, the P-type polycrystalline silicon resistor 117 includes a high resistance region 111 and high concentration impurity regions 109. A resistance value is set in accordance with the impurity concentration of the high resistance region.
For example, a sheet resistance value is dependent on a use of the resistor. In the case of a general voltage dividing circuit, the sheet resistance value from several kQ/square to several tens kQ/square is used. At this time, boron or BF2 is used as an impurity for the P−-type resistor 117 and the concentration thereof is about 1×1018 atoms/cm3. Phosphorus or arsenic is used as an impurity for the N-type resistor 116 and the concentration thereof is about 1×1014 to 9×1018 atoms/cm3.
Also, both the N-type resistor 116 and the P-type resistor 117 are shown in
Thus, when the gate electrode is set to be the P+-type, the PMOS transistor becomes the surface channel type PMOS transistor. Therefore, even when the threshold voltage is reduced, a leak current can be suppressed as compared with the buried channel type transistor. On the other hand, in the case of the NMOS transistor, when the gate electrode is set to be the P+-type, it becomes the buried channel type NMOS transistor. Here, arsenic having a smaller diffusion coefficient than boron is used as an impurity to be implanted for reducing the threshold voltage. Thus, the NMOS transistor becomes a state similar to the surface channel type transistor as compared with the PMOS transistor using an N+-type gate electrode. In addition, arsenic has the property of condensing near an interface between the silicon film and the oxide film. Therefore, the NMOS transistor further approaches a state similar to the surface channel type transistor. As a result, even when the threshold voltage is reduced in the N-type MOS transistor, a leak current can be suppressed and low voltage operation is possible. With respect to the homopolar gate structure, when the respective gate electrodes of the N-type MOS transistor and the P-type MOS transistor are set to be the P+-type, manufacturing steps are thereby simplified and costs can be reduced.
Further, in
The structure shown in
The difference of the amount of transverse diffusion toward a channel side between the light diffusion layers N 119 and P 120 and the heavy diffusion layers N+ 103 and P+ 104 is generally about 0.2 μm to 1 μm. In
From the above-mentioned description, a method of manufacturing the CMOS transistor using a P+-type polycrystalline silicon unipole as the gate electrode according to the present invention is a technique effective in low voltage operation and low power consumption as compared with a method of manufacturing a conventional CMOS transistor using an N+-type polycrystalline silicon unipole as the gate electrode. Further, the semiconductor device includes the polycrystalline silicon resistor different from the gate electrode and an offset structure transistor, thereby further enabling high grade function and high accuracy which are necessary for the analog circuit.
Next, steps of manufacturing the semiconductor device of the embodiment shown in
For example, phosphorus ions are implanted into the P-type silicon semiconductor substrate 101 and annealing is performed at 1000° C. to 1175° C. for 3 hours to 20 hours. Thus, the phosphorus ions are diffused to form the N-type well diffusion layer 102 having an impurity concentration of about 1×1016 atoms/cm3. Subsequently, the field insulating film 106 is formed by a LOCOS method, the gate insulating film 105 is formed at a film thickness of about 100 Å to 300 Å by thermal oxidation, and ion implantation is performed for obtaining a predetermined threshold voltage. After that, a first polycrystalline silicon film is deposited at a film thickness of about 500 Å to 2500 Å by a low pressure CVD method. Then, boron ions or BF2 ions are implanted into this first polycrystalline silicon film such that the impurity concentration thereof is equal to or higher than 1×1018 atoms/cm3, thereby forming the P+-type polycrystalline silicon film 107 (
Here, the P+-type polycrystalline silicon film is formed by ion implantation. However, the P+-type polycrystalline silicon film may be formed by a doped-CVD method of depositing a polycrystalline silicon film while an impurity such as boron is mixed thereinto at the same time. After that, a tungsten silicide film 112 as the high melting point metallic silicide film is deposited on the P+-type polycrystalline silicon film by a sputtering method or the like. Note that, here, the tungsten silicide film is used as the high melting point metallic silicide film. However, a molybdenum silicide film, a titanium silicide film, or a platinum silicide film can be also used. Then, the oxide insulating film 113 as a mask member for preventing introduction of an N-type impurity into a P+-type gate electrode is deposited on the high melting point metallic silicide film 112 at 500 Å to 3000 Å by the low pressure CVD method (
In addition, here, as the insulating film 113 on the P+-type gate electrode, an insulating film having a laminate structure of an oxide film having a film thickness of, for example, 300 Å, a nitride film having a film thickness of 500 Å, which is formed by a CVD method, and a thermal oxide film having a film thickness of about 10 Å may be formed for forming a high quality capacitor.
Next, as shown in
After that, as shown in
After that, the photo resist 119 is removed, and then patterning is performed using a photo resist and RIE anisotropic dry etching is performed, thereby forming the polycrystalline silicon resistor 116 having the N-type as the first conductivity type and the polycrystalline silicon resistor 117 having the P-type as the second conductivity type, as shown in
Next, as shown in
After the removal of the photo resist, as shown in
Next, as shown in
Then, after the photo resist is removed, as shown in
After that, although not shown, as in a conventional semiconductor process, formation of an intermediate insulating film, formation of contact holes, formation of an aluminum wiring pattern, and formation of a protective film and patterning thereof are performed to produce the complementary MOS semiconductor device.
Thus, the embodiment mode of the present invention is described based on the embodiment using the P-type semiconductor substrate. Even when the polarity of the substrate is reversed and the P+-type unipolar gate CMOS transistor of N-substrate P-well type is produced using the N-type semiconductor substrate, a semiconductor device achieving low voltage operation, low power consumption, and a low cost can be provided as in contents and principles as described above.
As described above, with respect to a power management semiconductor device and an analog semiconductor device which each include a CMOS transistor and a resistor, a manufacturing method of the present invention is a method of obtaining a P-type polycide structure as a laminate structure of a P-type polycrystalline silicon film and a high melting point metallic silicide film for the respective gate electrodes of both the NMOS transistor and the PMOS transistor as divided by the conductivity type thereof in the CMOS transistor, and further a semiconductor device manufacturing method in which a resistor used for a voltage dividing circuit and a CR circuit is formed by using a polycrystalline silicon film as a layer different from the gate electrode so that a higher accurate resistor can be obtained. Consequently, as compared with a conventional CMOS transistor having an N+-type polycrystalline silicon gate unipole and a conventional homopolar gate CMOS transistor in which the channel and the gate electrode have the same polarity, there is advantages in costs, manufacturing periods, and element performances. In addition, a power management semiconductor device and an analog semiconductor device which have high grade function and high accuracy can be realized.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2001-188050 | Jun 2001 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP02/06072 | 6/18/2002 | WO |
