BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a sectional view for explaining a method of manufacturing a semiconductor laser element according to First Embodiment of the present invention.
FIG. 2 is a sectional view for explaining a method of manufacturing a semiconductor laser element according to First Embodiment of the present invention.
FIG. 3 is a sectional view for explaining a method of manufacturing a semiconductor laser element according to First Embodiment of the present invention.
FIG. 4 is a sectional view for explaining a method of manufacturing a semiconductor laser element according to First Embodiment of the present invention.
FIG. 5 is a sectional view for explaining a method of manufacturing a semiconductor laser element according to First Embodiment of the present invention.
FIG. 6 is a diagram schematically showing the growing temperature and the transition of time of the growth of layers in burying and growing in the first embodiment.
FIG. 7 is a sectional view showing a semiconductor laser element manufactured using the manufacturing method according to the second embodiment of the present invention.
FIG. 8 is a sectional view for explaining a method of manufacturing a semiconductor laser element according to Third Embodiment of the present invention.
FIG. 9 is a diagram schematically showing the growing temperature and the transition of time of the growth of layers in burying and growing in the third embodiment.
FIG. 10 is a sectional view showing a semiconductor laser element wherein the circumference of the mesa in a semiconductor laminated structure having an active layer is buried with a structure laminated by n-type semiconductor layer, p-type semiconductor layer, n-type semiconductor layer and p-type semiconductor layer.
FIG. 11 is a sectional view showing a semiconductor laser element wherein an invalid current pathway wherein a current flowed from the mesa to the burying layers was formed.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment
The method for manufacturing a semiconductor laser element according to the first embodiment of the present invention will be described below referring to the drawings.
First, as FIG. 1 shows, a p-type InP clad layer 12, an AlGaInAs lower optical confinement layer 13, an AlGaInAs-MQW active layer 14, an n-type AlGaInAs upper optical confinement layer 15, and an n-type InP clad layer 16 are sequentially grown on a p-type InP substrate 11 using crystal growth by metal organic vapor phase epitaxy (MOVPE) to form a semiconductor laminated structure having an active layer composed of an Al-containing semiconductor material, AlxGayIn1-x-yAs (0<x<1, 0<y<1).
Next, as FIG. 2 shows, the wafer is taken out from the MOVPE apparatus, an SiO2 film is formed on the wafer to fabricate an SiO2 mask 25 using photo lithograpy and transfer processes. Then, wet etching is performed using the SiO2 mask 25 as a mask to form a mesa of the semiconductor laminated structure as shown in FIG. 3. At this time, an inversely tapered portion may be formed on the side of the mesa due to difference of the semiconductor layers to be etched or etching conditions.
Next, the wafer on which the mesa has been formed is placed again in the MOVPE apparatus, and as FIG. 4 shows, a p-type InP first burying layer 17a (first burying layer) is formed at a growing temperature of Tg_p1 (first growing temperature) so as to coat the side of the mesa, and on the p-type InP first burying layer 17a, a p-type InP second burying layer 17b, an n-type InP current blocking layer 18, a p-type InP burying layer 19, and an n-type InP burying layer 20 (second burying layer) are formed at a growing temperature of Tg_p2 (second growing temperature) to bury the circumference of the mesa.
Next, as FIG. 5 shows, the wafer is taken out from the MOVPE apparatus, and the mask 25 is etched off. Thereafter the wafer is placed again in the MOVPE apparatus, and an n-type InP contact layer 21, an n-type InGaAs contact layer 22, and an n-type InP cap layer 23 are formed. By the above-described manufacturing process, a semiconductor laser element having an n/p/n/p buried structure is manufactured.
Here, FIG. 6 is a diagram schematically showing the growing temperature and the transition of time of the growth of layers in burying and growing in the first embodiment. As FIG. 6 shows, the growing temperature Tg_p1 for the p-type InP first burying layer 17a is lower than the growing temperature Tg_p2 for the p-type InP second burying layer 17b (Tg_p1<Tg_p2). It is preferable in view of crystal qualities that the growing temperatures for the layers other than the p-type InP first burying layer 17a are within a range between 600° C. and 630° C., which is the to be optimal for InP growth by MOVPE.
As described above, since the growing temperature Tg_p1 for the p-type InP first burying layer 17a contacting the mesa is lower than the growing temperature Tg_p2 for the p-type InP second burying layer 17b, the migration of growing species on the side of the mesa is suppressed, and the inversely tapered portion of the mesa is also coated with the p-type InP first burying layer 17a. Thereby, since the n-type InP current blocking layer 18 can be grown without contacting the mesa, the formation of an invalid current pathway can be prevented.
In the first embodiment, although the p-type InP burying layer is divided into two burying layers, the p-type InP first burying layer 17a and the p-type InP second burying layer 17b, the p-type InP burying layer can be divided into more than two (n) layers. At this time, the growing temperature Tg_p1 for the p-type InP first burying layer 17a should be lower than the growing temperature Tg_pm for the p-type InP mth burying layer (1<m<n).
Although growth is interrupted between the growth of the p-type InP first burying layer 17a and the growth of the p-type InP second burying layer 17b, the growing temperatures of the burying growth can be continuously elevated from Tg_p1 to Tg_p2 while growing from the p-type InP first burying layer 17a to the p-type InP second burying layer 17b without interrupting growth.
The present invention is not limited to the burying growth of a structure laminated by n-type semiconductor layer, p-type semiconductor layer, n-type semiconductor layer and p-type semiconductor layer, but can be applied to any burying growth. The present invention can also be applied to the burying growth of a mesa in a semiconductor laminated structure composed of any semiconductor materials, such as InP, AlGaInAs, InGaAs, InGaAsP, AlInAs, AlGaAs, GaAs, AlGaInP, InGaP, AlGaN, GaN, and InGaN. The optimal growing temperatures for the growth of these semiconductor materials are: 600 to 630° C. for InP, InGaAsP, and InGaAs; 600 to 750° C. for AlGaInAs and AlInAs; 650 to 750° C. for AlGaAs, GaAs, AlGaInP and InGaP; 1000 to 1100° C. for AlGaN and GaN; and 700 to 800° C. for InGaN. When the present invention is applied to the burying growth using these materials, it is desirable that the growing temperature of the first burying layer is lower than these optimal growing temperatures. The present invention can be applied not only to the fabrication of a semiconductor laser, but also to the fabrication of any semiconductor elements, such as a modulator and a photo detector.
Second Embodiment
FIG. 7 is a sectional view showing a semiconductor laser element manufactured using the manufacturing method according to the second embodiment of the present invention. The second embodiment differs from the first embodiment in that the mesa is formed by dry etching, and the shape of the mesa differs from that of the first embodiment. Other constitutions, for example, the sequence of burying growth and the temperature setting for burying growth, are the same as in the first embodiment.
Also in a mesa having a different shape formed by dry etching, the migration of the growing species can be suppressed by growing the first burying layer at a low temperature, and the side of the mesa having an inversely tapered portion can be coated. Thereby, since an n-type InP current blocking layer 18 can be grown without contacting the mesa, the formation of an invalid current pathway can be prevented.
Third Embodiment
The method for manufacturing a semiconductor laser element according to the third embodiment of the present invention will be described below referring to the drawings. First, as in the first embodiment, and as FIGS. 1 to 3 show, a semiconductor laminated structure having an active layer composed of an Al-containing semiconductor material, AlxGayIn1-x-yAs (0<x<1, 0<y<1) is formed, and then, the semiconductor laminated structure is etched to form a mesa.
Next, the wafer on which the mesa has been formed is placed again in the MOVPE apparatus and the side of the mesa is cleaned by HCl gas, which has an etching effect. Thereafter, as FIG. 8 shows, a p-type InP first burying layer 17a (first burying layer) is formed at a growing temperature of Tg_p1 (first growing temperature) so as to coat the side of the mesa, and on the p-type InP first burying layer 17a, a p-type InP second burying layer 17b, an n-type InP current blocking layer 18, an Fe—InP current blocking layer 26, and an n-type InP burying layer 20 (second burying layer) are formed at a growing temperature of Tg_p2 (second growing temperature) to bury the circumference of the mesa. Then, the wafer is taken out from the MOVPE apparatus and the mask 25 is etched off. Thereafter, the wafer is placed in the MOVPE apparatus again, and an n-type InP contact layer 21, an n-type InGaAs contact layer 22, and an n-type InP cap layer 23 are grown. By the above-described manufacturing process, a semiconductor laser element having a buried structure laminated by n-type semiconductor layer, Fe-doped semiconductor layer, n-type semiconductor layer and p-type semiconductor layer is manufactured.
Here, FIG. 9 is a diagram schematically showing the growing temperature and the transition of time of the growth of layers in burying and growing in the third embodiment. As FIG. 9 shows, the wafer is heated to the etching temperature T_etch, and the etching process is carried out by introducing HCl gas. Then, the temperature is lowered to the growing temperature Tg_p1 of the p-type InP first burying layer 17a. Here, the temperature T_etch of the etching process using HCl gas is higher than the growing temperature Tg_p1 of the p-type InP first burying layer 17a (T_etch>Tg_p1). Thereby, the firm oxide film on the side of an AlGaInAs layer exposed on the side of the mesa at the time of the formation of the mesa becomes easy to remove.
Also as in the first embodiment, since the growing temperature Tg_p1 of the p-type InP first burying layer 17a contacting the mesa is lower than the growing temperature Tg_p2 of the p-type InP second burying layer 17b, the migration of the growing species on the side of the mesa is suppressed, and the side of the active layer composed of an oxidizable AlGaInAs material can coat the circumference of the mesa without defective burying, such as pitted growth. Thereby, since the n-type InP current blocking layer 18 or the Fe—InP current blocking layer can be grown without contacting the mesa, the formation of an invalid current pathway can be prevented.
In the third embodiment, although HCl gas is used, other gases having an etching effect, such as TBCl and CCl4 can also be used in the etching step before burying growth. The present invention is not limited to the burying growth of a structure laminated by n-type semiconductor layer, Fe-doped semiconductor layer, n-type semiconductor layer and p-type semiconductor layer, but can be applied to any burying growth.
Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.
The entire disclosure of a Japanese Patent Application No. 2006-209744, filed on Aug. 1, 2006 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.
Patent Application
20080032435
